• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.10C
• /
• pp.1019-1024
• /
• 2007

In this paper, the 10bit 20MHz pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.6
• /
• pp.98-106
• /
• 1994

To realize high accuracy and high speed we developed a new self compensation scheme and applied it to a 10-bit D/A converter. This circuit can compensate the device mismatch without interrupting the D/A converter operation. With the compensation circuit,INA decreased down to 0.22LSB from 0.47LSB. The device was fabricated using a 0.8$\mu$m CMOS process. The area of the D/A converter core is 3.2mm$^{2}$ and the area of the compensation part is 0.64mm$^{2}$.

• Journal of Power Electronics
• /
• v.14 no.4
• /
• pp.641-648
• /
• 2014

This paper presents the design considerations and analysis for an interleaved boundary conduction mode power factor correction buck converter. A thorough analysis of the harmonic content of the AC line current is presented to examine the allowable voltage gain (K value) for meeting the EN61000-3-2, Class D standard while maximizing efficiency. The results of the harmonic analysis are used to derive the required value of K and therefore the output voltage necessary to meet the class D requirements for a given AC line voltage. The discussed design consideration and harmonic current analysis are verified on a 300W universal line experimental prototype converter with an 80V output. The measured efficiencies remain above 96% down to 20% of the full load. The input current harmonics also meet the IEC61000-3-2 (class D) standard.

• Journal of Power Electronics
• /
• v.15 no.4
• /
• pp.886-898
• /
• 2015

The design feasibility of a micro unidirectional DC transmission system based on an input-parallel output-parallel (IPOP) converter is analyzed in this paper. The system consists of two subsystems: an input-parallel output-series (IPOS) subsystem to step up the DC link voltage, and an input-series output-parallel (ISOP) subsystem to step down the output voltage. The two systems are connected through a transmission line. The challenge of the delay caused by the communication in the control system is addressed by introducing a ring communication structure, and its influence on the control system is analyzed to ensure the feasibility and required performance of the converter system under practical circumstances. Simulation and experiment results are presented to verify the effectiveness of the proposed design.

• Proceedings of the KIPE Conference
• /
• 2008.10a
• /
• pp.45-47
• /
• 2008

This paper describes development of PMSG wind power system model using wind turbine simulator and matrix converter. The wind turbine simulator, which consists of an induction motor with vector drive, calculates the output torque of a specific wind turbine using simulation software and sends the torque signal to the vector drive after scaling down the calculated value. The operational feasibility of interconnected PMSG system with matrix converter was verified by computer simulations with PSCAD/EMTDC software. The simulation results confirm that matrix converter can be effectively applied for the PMSG system.

• Proceedings of the KIEE Conference
• /
• 1998.11a
• /
• pp.115-116
• /
• 1998

A flyback converter that decreases ZVS resonant voltage by using ZVS capacitor is proposed. Because of high resonant voltage at ZVS convenient circuits use expensive devices of high power. The devices make the total price high. A circuit with ZVS capacitor is proposed to down the price. A practical converter can be constructed. Operation of the converter is analyzed and simulated. We compare experiment results with simulation results. We show that the system is identical with the simulated system.

• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.82-88
• /
• 2009

This paper is analyzed for a step up-down DC/DC chopper of high efficiency added electric isolation. The converters of high efficiency are generally made that the power loss of the used semiconductor switching devices is minimized. To achieve high efficiency system, the proposed chopper is constructed by using a partial resonant circuit. The control switches using in the chopper are operated with soft switching by partial resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the chopper is high. The proposed chopper is also added electric isolation which is used a pulse transformer. When the power conversion system is required electric isolation, the proposed chopper is adopted with the converter system development of high efficiency. The soft switching operation and the system efficiency of the proposed chopper are verified by digital simulation and experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.10a
• /
• pp.196-199
• /
• 2000

In this paper, we have designed a low-noise amplifier for the down-converter to apply the K-band Mu-kung-hwa satellite downconvertion. We have designed on three-stage to satisfy the property of low-noise amplifier for the down-converter required at least 30dB gain. The simulaition results for the designed three-stage Low-noise amplifier are measured that 33dB, gain and 0.93dB, noise-figure From 19.200 to 20.200, and The experiment results of the fabric are measured that 25dB, gain and 1.5dB, noise-figure. Since Input reflection coefficient and otput resection coefficient are -25dB and -28dB, respectively, and VSWR is lower than 1.5, this amplifier can be used as a low-noise amplifier for the down-converter to apply the K-band Mu-kung-hwa satellite downconvertion.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.38 no.2
• /
• pp.38-49
• /
• 2001

This paper presents a new voltage down converter(VDC) using charge and discharge current adjustment circuitry that provides high frequency application. This VDC consist of a common driving circuit and compensation circuits: 2 sensors and each driving transistors for controlling gate current of driving transistor. These sensors are operated as adaptive biasing method with high speed and low power consumption. This circuit is designed with a $0.62{\mu}m$ N well CMOS technology. In H-spice simulation results, internal voltage is bounded ( IV, +0.6V) in proposed circuitry when load current rapidly increases and decreases during Gns between 0 and $200m{\Lambda}$. And the recovery time of internal voltage is about 7ns and 10ns when load current increases and decreases respectively. That is fast better than common driving circuit. Total power consumption is about 1.2mW.

• 전자공학회논문지 IE
• /
• v.45 no.1
• /
• pp.31-37
• /
• 2008

A Wibro RF down converter of 2.3GHz band is designed and implemented in this paper. The problems that can occur in the receiver LNA(Low Noise Amplifier) to minimize additional purposes. In addition, 2.3GHz band from the 75 MHz downward to minimize the losses in the process, transform and improve efficiency, and achieve stable characteristics can be used to make high frequency characteristics of the device. Wibro repeater uses a TDMA(Time Division Multiplexing Access) method is needed because the RF switch. Production criterion specification, the input voltage from +8 V 1.2A of current consumption, 60dB gain and the noise figure of less than 2.5dB, VSWR(Voltage Standing Wave Ratio) less than 1.5, more than IMD(Inter Modulation Distortion) 60dB satisfied. Environmental conditions ($-20^{\circ}C$ to $70^{\circ}C$) to pass the test of reliability in a long time, that seemed crafted Wibro down converter be applied to the Wibro repeater.