• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2004년도 추계학술발표대회 개요집
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• pp.123-124
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• 2004

This study was investigated on the impact toughness and microstructure of welded metal and heat affected zone for Hi Nitrogen TiN Steel. With welding procedures, welding heat input applied were 30, 79 and 264 kJ/cm. TiN steel has shown very small prior austenite grain size for all the welding heat input applied, which was considered to result from the effect of TiN particles. In case of single SAW and EGW welding, the dilution rate of base metal into the weld was not high, resulting that there were no significant effects of base metal chemical composition on the mechanical properties of welds. However, TSAW with double Ypreparation carried very high dilution rate so that TiN steel has impaired the toughness of weld metal because N content in the weld was increased through the dilution of base metal.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.264-267
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• 1993

A high plasma density of $10^{12}cm^{-3}$ can be produced at the pressure of few mTorr with R. F input power of 300-400W. A radially uniform plasma to a radius of 7cm at the substrate was produced at the pressure of 1 mTorr. The electron density and temperature were confirmed with double Langmuir probe, $\mu$-wave interferometer. It has bee found that the dispersion relation N/B=constant not be applied at the low R.F input power(<600W) but can be applied at high R.F input power(>600W).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.755-758
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• 2002

This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary N- and P-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors far the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 ${\mu}$m n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing ${\pm}$2.4 V under ${\pm}$2.5 V power supplies and shows the exact voltage and current following performances up to 100 MHz. Because of its high performances, the CCII proposed herein is quite useful for a building block of current-mode circuits. The applications of the proposed CCII to current-mode filters are also described.

• Journal of Power Electronics
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• 제14권4호
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• pp.778-787
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• 2014

This study presents an input filter resonance mitigation method for an AC-DC matrix converter. This method combines the advantages of the one-cycle control strategy and the active damping technique. Unnecessary sensors are removed, and system cost is reduced by employing the grid-side input currents as feedback to damp out LC resonance. A model that includes the proposed method and the input filter is established with consideration of the delay caused by the actual controller. A zero-pole map is employed to analyze model stability and to investigate virtual resistor parameter design principles. Based on a double closed-loop control scheme, the one-cycle control strategy does not require any complex modulation index control. Thus, this strategy can be more easily implemented than traditional space vector-based methods. Experimental results demonstrate the veracity of theoretical analysis and the feasibility of the proposed approach.

• 한국전자파학회논문지
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• 제14권9호
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• pp.944-949
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• 2003

본 논문에서는 InCaP/GaAs HBT공정을 이용하여 낮은 DC 파워소모, 낮은 NF, 낮은 IMD 와 광대역 특성을 갖는 Ku-band LNB용 이중평형믹서를 설계하였다. 제작된 믹서는 3 V, 16 mA 의 U조건과 -23 dBm의 RF입력 조건하에서 5 dB의 변환이득, 14 dB의 NF, 17.9 GHz의 대역폭 그리고 50.34 dBc의 IMD특성을 얻었다. 낮은 IMD 특성, 광대역폭, 낮은 파워소모 특성은 InGaP/GaAs HBT의 선형성과 광대역 입력 정합기법과 바이어스 점의 최적화를 통해 얻을 수 있었다.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.7-15
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• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2008년도 춘계 학술발표회 초청강연 및 논문집
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• pp.281-292
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• 2008

Prefabricated Board Drains (PBDs) recently become more widely used than conventional sand drains in improving soft ground because the PBD is more time and cost effective. The performance of PBDs is affected by disturbance in the adjacent soil formation during inserting mandrels, the intrusion of fine particles into filter fabric, and necking of the drain by excessive lateral pressure especially occurring in very deep clay formation such as the Busan New Port site. In this study, the PBD with double-core is introduced, which seems to overcome the shortcomings of usual single-core PBDs. An in-situ test program was established in the Busan New Port site, in which a set of the double-core PBDs and the single-core PBDs was installed to compare the efficiency of each of the drains. The discharge capacity of the double-core and the single-core PBDs was compared for various confining pressures in the modified Delft test and the chamber test. A series of CRS consolidation tests was performed in order to obtain profiles of void ratio-effective stress and void ratio-permeability relationships in the Busan New Port site that are used as input date in performing a numerical program ILLICON. The numerically simulated settlements of ground surface in the test site are in good agreement with those of in-situ measurements. In addition, the performance of the double-core and single-core PBDs has been experimentally and numerically compared in this paper.

• Earthquakes and Structures
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• 제9권6호
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• pp.1133-1152
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• 2015

A frequency-domain method is developed for evaluating the earthquake input energy to two building structures connected by viscous dampers. It is shown that the earthquake input energies to respective building structures and viscous connecting dampers can be defined as works done by the boundary forces between the subsystems on their corresponding displacements. It is demonstrated that the proposed energy transfer function is very useful for clear understanding of dependence of energy consumption ratios in respective buildings and connecting viscous dampers on their properties. It can be shown that the area of the energy transfer function for the total system is constant regardless of natural period and damping ratio because the constant Fourier amplitude of the input acceleration, relating directly the area of the energy transfer function to the input energy, indicates the Dirac delta function and only an initial velocity (kinetic energy) is given in this case. Owing to the constant area property of the energy transfer functions, the total input energy to the overall system including both buildings and connecting viscous dampers is approximately constant regardless of the quantity of connecting viscous dampers. This property leads to an advantageous feature that, if the energy consumption in the connecting viscous dampers increases, the input energies to the buildings can be reduced drastically. For the worst case analysis, critical excitation problems with respect to the impulse interval for double impulse (simplification of pulse-type impulsive ground motion) and multiple impulses (simplification of long-duration ground motion) are considered and their solutions are provided.

• 센서학회지
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• 제11권5호
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• pp.255-262
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• 2002

인간의 망막은 효율적으로 주어진 물체의 윤곽을 검출할 수 있다. 본 연구에서는 윤곽검출에 관여하는 망막 세포의 기능을 전자회로로 모델링하여 윤곽검출기능을 가지는 CMOS 시각칩을 설계하였다. CMOS 제조공정 중에는 여러 가지 요인에 의해 MOSFET의 특성이 변화할 수 있으며, 특히 어레이로 구성되어 각 픽셀의 신호를 출력하는 readout 회로에서의 특성변화는 출력옵셋으로 나타난다. 하드웨어로 입력영상의 윤곽을 검출하는 시각칩은 다른 응용시스템의 입력단에 사용되므로 이러한 옵셋은 전체 시스템의 성능을 결정하는 중요한 요소이다. 본 연구에서는 이와 같은 출력단의 옵셋을 제거하기 위해 CDS(Correlated Double Sampling) 회로를 이용한 윤곽 검출용 시각칩을 설계하였다. 설계된 시각칩은 CMOS 표준공정을 이용하여 다른 회로와 집적화가 가능하며, 기존의 시각칩보다 신뢰성 있는 출력특성을 나타냄으로써, 물체의 윤곽을 이용하는 물체추적, 지문인식, 인간 친화적 로봇시스템등의 다양한 응용 시스템의 입력단으로 적용될 수 있을 것이다.

• 융합정보논문지
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• 제12권3호
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• pp.38-45
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• 2022

핀테크 기술의 발전으로 인해 스마트폰을 이용한 금융거래가 활성화되고 있다. 금융거래시 사용자 인증을 위한 비밀번호는 스마트 폰의 터치 스크린 상에 보여지는 가상 키패드를 통해 입력된다. 비밀번호를 터치할 때 공격자가 높은 해상도를 가진 카메라로 촬영하거나 어깨 너머로 훔쳐보는 방식으로 사용자가 입력한 비밀번호를 알아낼 수 있다. 이런 공격을 막기 위해 보안이 적용된 가상 키패드는 크기가 작은 터치 스크린에 입력하기 어렵고, 훔쳐보기 공격에 취약점이 여전히 존재한다. 본 논문에서는 전체 키패드를 몇 개의 그룹으로 나누고 작은 화면에 표시하여 입력할 문자가 속해 있는 그룹을 터치하고, 그룹 내에서 해당 문자를 터치하는 방식으로 입력할 문자를 쉽게 찾을 수 있다. 제안기법은 입력할 문자가 속한 그룹을 선택하며 해당 그룹에 키패드를 10개 이내로 작은 스크린에 보여주기 때문에 키패드의 크기를 기존 방법보다 2배 이상 확대가 가능하고, 위치를 랜덤하게 배치하여 터치한 위치를 통한 공격을 차단할 수 있다.