• Title/Summary/Keyword: Double slope

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A Study on the Change of Heat Transmission Coefficient According to the Degree of Windows Slope (창의 경사도에 따른 열관류율 변화에 관한 연구)

  • 황하진;이경희
    • Journal of the Korean housing association
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    • v.12 no.3
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    • pp.133-140
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    • 2001
  • This study investigated the heat transmission coefficient through the experiment that the skylight, slope window of 60 degree and 30 degree consisted of pair glass and the double window of external window and internal window paper were suitable for heat insulation. As the result of experiment, the heat transmission coefficient of slope window was 1.06 times in the 60 degree, 1.18 times in the 30 degree and 1.31 times in the skylight as a standard lateral window. The heat transmission coefficient in the double window of external window and internal window paper was 3.017$\textrm{㎉}$/$\textrm{m}^2$.hr.$^{\cire}C$. The slope window was not suitable for the prescription by the increase of the heat transmission coefficient, so the user must pay attention to the treatment. This study investigated only the slope window of 12mm and 16mm pair glass and the double window of external window and internal window paper, study on the various pattern of window must be achived in a future.

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Characteristics analysis of Sub-50nm Double Gate MOSFET (Sub-50nm Double Gate MOSFET의 특성 분석)

  • 김근호;고석웅;이종인;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.486-489
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    • 2002
  • In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

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Optimization of Side Gate in the Design for Nano Structure Double Gate MOSFET (나노 구조 Double Gate MOSFET 설계시 side gate의 최적화)

  • 김재홍;고석웅;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.490-493
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    • 2002
  • In this study, we have investigated optimum value for side gate length and side gate voltage of double gate (DG) MOSFET with main gate and side gate. We know that optimum side gate voltage for each side length is about 3V. Also, we know that optimum side gate length for each main gate length is about 70nm. We have presented the transconductance and subthreshold slope for each side gate length. We have simulated using ISE-TCAD tool for characteristics analysis of device.

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Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC (10-bit Two-Step Single Slope A/D 변환기를 이용한 고속 CMOS Image Sensor의 설계)

  • Hwang, Inkyung;Kim, Daeyun;Song, Minkyu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.64-69
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    • 2013
  • In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

  • Hwang, Yeonseong;Song, Minkyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.246-251
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    • 2014
  • In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

An Improved SPIHT Algorithm based on Double Significance Criteria

  • Yang, Chang-Mo;Ho, Yo-Sung
    • Proceedings of the IEEK Conference
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    • 2000.07b
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    • pp.910-913
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    • 2000
  • In this paper, we propose an improved SBIHT algorithm based on double significance criteria. According to the defined relationship between a threshold and a boundary rate-distortion slope, we choose significant coefficients and trees. The selected significant coefficients and trees are quantized and entropy-coded. Experimental results demonstrate that the boundary rate-distortion slope is well adapted and the proposed algorithm is quite competitive to and often outperforms the SPIHT algorithm.

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Design of a Comparator with Improved Noise and Delay for a CMOS Single-Slope ADC with Dual CDS Scheme (Dual CDS를 수행하는 CMOS 단일 슬로프 ADC를 위한 개선된 잡음 및 지연시간을 가지는 비교기 설계)

  • Heon-Bin Jang;Jimin Cheon
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.6
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    • pp.465-471
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    • 2023
  • This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

Development of Optimum Structural Design System for Double Hull Oil Tankers (이중 선각 유조선의 최적 구조 설계 시스템 개발)

  • Chang-Doo Jang;Seung-Soo Na
    • Journal of the Society of Naval Architects of Korea
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    • v.37 no.1
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    • pp.118-126
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    • 2000
  • An optimum structural design system for double hull oil tankers is developed based on the generalized slope deflection method which was previously proposed by the authors. For the optimization technique, the Hooke & Jeeves direct search method is applied to the minimum weight design problems with discrete design variables. A minimum weight design program is developed for the longitudinal members by the classification rules and for the transverse frames and the bulkhead members by the generalized slope deflection method. By this program, a minimum hull weight design of double hull oil tankers considering tank arrangement is performed and the design results are compared with existing ship. It is possible to find optimum tank arrangement and efficient types of hull structures for the minimum weight design of double hull oil tankers.

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Analysis of Double Gate MOSFET characteristics for High speed operation (초고속 동작을 위한 더블 게이트 MOSFET 특성 분석)

  • 정학기;김재홍
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.2
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    • pp.263-268
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    • 2003
  • In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (NG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 3V in the main gate 50nm. Also, we know that optimum side gate length for each for main gate length is about 70nm. DG MOSFET shows a small threshold voltage roll-off. From the I-V characteristics, we obtained IDsat=550$mutextrm{A}$/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86.2㎷/decade, transconductance is 114$mutextrm{A}$/${\mu}{\textrm}{m}$ and DIBL (Drain Induced Barrier Lowering) is 43.37㎷. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Then, we have obtained very high cut-off frequency of 41.4GHz in the DG MOSFET.

The expanded LE Morgenstern-Price method for slope stability analysis based on a force-displacement coupled mode

  • Deng, Dong-ping;Lu, Kuan;Wen, Sha-sha;Li, Liang
    • Geomechanics and Engineering
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    • v.23 no.4
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    • pp.313-325
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    • 2020
  • Slope displacement and factor of safety (FOS) of a slope are two aspects that reflect the stability of a slope. However, the traditional limit equilibrium (LE) methods only give the result of the slope FOS and cannot be used to solve for the slope displacement. Therefore, developing a LE method to obtain the results of the slope FOS and slope displacement has significance for engineering applications. Based on a force-displacement coupled mode, this work expands the LE Morgenstern-Price (M-P) method. Except for the mechanical equilibrium conditions of a sliding body adopted in the traditional M-P method, the present method introduces a nonlinear model of the shear stress and shear displacement. Moreover, the energy equation satisfied by a sliding body under a small slope displacement is also applied. Therefore, the double solutions of the slope FOS and horizontal slope displacement are established. Furthermore, the flow chart for the expanded LE M-P method is given. By comparisons and analyses of slope examples, the present method has close results with previous research and numerical simulation methods, thus verifying the feasibility of the present method. Thereafter, from the parametric analysis, the following conclusions are obtained: (1) the shear displacement parameters of the soil affect the horizontal slope displacement but have little effect on the slope FOS; and (2) the curves of the horizontal slope displacement vs. the minimum slope FOS could be fitted by a hyperbolic model, which would be beneficial to obtain the horizontal slope displacement for the slope in the critical state.