• 제목/요약/키워드: Double gate

검색결과 375건 처리시간 0.029초

AlGaAs/GaAs/AlGaAs 이중 이종집합 HEMT 구조에서의 2차원 전자개스 농도의 양자역학적 계산 (Quantum Mechanical Calculation of Two-Dimensional Electron Gas Density in AlGaAs/GaAs/AlGaAs Double-Heterojunction HEMT Structures)

  • 윤경식;이정일;강광남
    • 전자공학회논문지A
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    • 제29A권3호
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    • pp.59-65
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    • 1992
  • In this paper, the Numerov method is applied to solve the Schroedinger equation for $Al_{0.3}Ga_{0.7}AS/GaAs/Al_{0.3}Ga_{0.7}As$ double-heterojunction HEMT structures. The 3 subband energy levels, corresponding wave functions, 2-dimensional electron gas density, and conduction band edge profile are calculated from a self-consistent iterative solution of the Schroedinger equation and the Poisson equation. In addition, 2-dimensional electron gas densities in a quantum well of double heterostructure are calculated as a function of applied gate voltage. The density in the double heterojunction quantum well is increased to about more than 90%, however, the transconductance of the double heterostructure HEMT is not improved compared to that of the single heterostructure HEMT. Thus, double-heterojunction structures are expected to be suitable to increase the current capability in a HEMT device or a power HEMT structure.

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Analysis of Subthreshold Characteristics for Device Parameter of DGMOSFET Using Gaussian Function

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • 제9권6호
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    • pp.733-737
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    • 2011
  • This paper has studied subthreshold characteristics for double gate(DG) MOSFET using Gaussian function in solving Poisson's equation. Typical two dimensional analytical transport models have been presented for symmetrical Double Gate MOSFETs (DGMOSFETs). Subthreshold swing and threshold voltage are very important factors for digital devices because of determination of ON and OFF. In general, subthreshold swings have to be under 100mV/dec, and threshold voltage roll-off small in short channel devices. These models are used to obtain the change of subthreshold swings and threshold voltage for DGMOSFET according to channel doping profiles. Also subthreshold swings and threshold voltages have been analyzed for device parameters such as channel length, channel thickness and channel doping profiles.

Symmetric and Asymmetric Double Gate MOSFET Modeling

  • Abebe, H.;Cumberbatch, E.;Morris, H.;Tyree, V.;Numata, T.; Uno, S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제9권4호
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    • pp.225-232
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    • 2009
  • An analytical compact model for the asymmetric lightly doped Double Gate (DG) MOSFET is presented. The model is developed using the Lambert Function and a 2-dimensional (2-D) parabolic electrostatic potential approximation. Compact models of the net charge and channel current of the DG-MOSFET are derived in section 2. Results for the channel potential and current are compared with 2-D numerical data for a lightly doped DG MOSFET in section 3, showing very good agreement.

반도체(半導體) DI switching소자(素子)의 전기적(電氣的) 특성(特性) (Electrical Characteristics of Semiconductor DI Switching Devices)

  • 정세진;임경문;성만영
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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    • pp.110-114
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    • 1990
  • Double Injection Switching Devices consist of $P^+$ and $n^+$ contact separated by a near intrinsic Semiconductor region containing deep trap. A V-Groove Double Injection Switching Devices were proposed for high voltage performance and Optical gating scheme. The experimental result to demonstrate the feasibility of these devices (Planar type, V-Groove type, Injection Gate mode, Optical Gate mode) for practical application are described.

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Nanoscale NAND SONOS memory devices including a Seperated double-gate FinFET structure

  • Kim, Hyun-Joo;Kim, Kyeong-Rok;Kwack, Kae-Dal
    • 한국신뢰성학회지:신뢰성응용연구
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    • 제10권1호
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    • pp.65-71
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    • 2010
  • NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

Electrical Analysis of Bottom Gate TFT with Novel Process Architecture

  • Pak, Sang-Hoon;Jeong, Tae-Hoon;Kim, Si-Joon;Kim, Kyung-Ho;Kim, Hyun-Jae
    • Journal of Information Display
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    • 제9권2호
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    • pp.5-8
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    • 2008
  • Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a-Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a-Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a-Si TFTs. The threshold voltage shift of DAL TFTs and a-Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a-Si TFTs.

급수를 이용한 DGMOSFET의 DIBL 특성 분석 (Analysis of DIBL Characteristics for Double Gate MOSFET Using Series)

  • 한지형;정학기;정동수;이종인;권오신
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2011년도 춘계학술대회
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    • pp.709-711
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    • 2011
  • 본 연구에서는 Double-gate MOSFET의 DIBL(Drain Induced Barrier Lowering)의 특성을 분석하기 위하여 분석학적 전송모델을 사용하였으며 분석학적 모델을 유도하기 위하여 포아송방정식을 풀 때 급수함수를 이용하였다. 단채널 효과에서는 유효채널길이 감소와 문턱전압 감소 그리고 DIBL이 있다. DIBL은 드레인 전압 변화에 따른 문턱전압의 변화로 알 수 있다. 채널길이가 감소하면 DIBL은 감소하지만, 채널길이가 감소하면 단채널 효과가 증가한다. 본 논문에서는 채널길이에 따른 DIBL을 분석하였고, 또한 채널 두께 및 게이트 산화막의 두께에 대한 DIBL에 대하여 분석하였다.

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An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

  • Arun Samuel, T.S.;Balamurugan, N.B.
    • Journal of Electrical Engineering and Technology
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    • 제9권1호
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    • pp.247-253
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    • 2014
  • In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

더블 게이트 구조의 탄소 나노 튜브 트랜지스터 바이오 센서의 제작 (Fabrication of the CNT-FET biosensors with a double-gate structure)

  • 조병현;임병현;신장규;최성욱;전향숙
    • 센서학회지
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    • 제18권2호
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    • pp.168-172
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    • 2009
  • In this paper, we present the carbon nanotube field-effect transistor(CNT-FET) with a double-gate structure. A Carbon nanotube film was aligned by the Langmuir-Blodgett technique and $SiN_x$ was deposited to protect from water, oxygen, and other contaminants. We measured the electrical characteristics of the proposed device as the function of the $V_{BG}$, $V_{TG}$. From this result, we can confirm that proposed device might be employed as a biosensor.

Electrical Properties of Bottom-Contact Organic Thin-Film-Transistors with Double Polymer Gate Dielectric Layers

  • Hyung, Gun-Woo;Park, Il-Houng;Choi, Hak-Bum;Hwang, Sun-Wook;Kim, Young-Kwan
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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    • pp.264-264
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    • 2008
  • We fabricated a pentacene thin-film transistor with a Polymer/$SiO_2$ Double Gate Dielectrics and obtained a device with better electrical characteristics. This device was found to have a field-effect mobility of $0.04cm^2$/Vs, a threshold voltage of -2V, an subthreshold slope of 1.3 V/decade, and an on/off current ratio of $10^7$.

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