• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.2
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• pp.63-68
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• 2005

Total 12 units of high power klystron-modulator systems as microwave source are under operation for 2.5 GeV electron linear accelerator in Pohang Light Source (PLS) linac. The klystron-modulator system has an important role for the stable operation to improve an availability statistics of overall system performance of klystron-modulator system. RF power and beam power of klystron are precisely measured for the effective control of electron beam. A precise measurement and measurement equipment with good response characteristics are demanded for this. Input power of klystron is calculated from the applied voltage and the current on its cathode. Tiny measurement error severely effects RF output power value of klystron. Therefore, special care is needed to measure precise beam voltage. Capacitive voltage divider (CVD), which divides input voltage as capacitance ratio, is intended for the measurement of a beam voltage of 400 kV generated from the klystron-modulator system. Main parameter to determine standard capacitance in the high arm of CVD is dielectric constant of insulation oil. Therefore CVD should be designed to have a minimum capacitance variation due to voltage, frequency and temperature in the measurement range. This paper will be present and discuss the design concept and analysis of capacitive voltage divider for a pulsed high-voltage measurement, and the empirical relations between capacitance effects and oil temperature variation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.66-73
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• 2002

As floating-point operations become widely used in various applications such as computer graphics and high-definition DSP, the needs for fast division become increased. However, conventional floating-point dividers occupy a large hardware area, and bring bottle-becks to the entire floating-point operations. In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors, is designed using he series expansion algorithm. The algorithm is selected to utilize two MAC(Multiply-ACcumulate) units for quadratic convergence to the correct quotient. The two MAC units for SIMD-DSP features are shared and the additional area for the division only is very small. The proposed divider supports all rounding modes defined by IEEE 754 standard, and error estimations are performed for appropriate precision.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.633-637
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• 2005

In this contribution, we developed and improved an existing GF (Galois field) dividing algorithm by suggesting a novel architecture for a finite field divider, which is frequently required for the error correction applications and the security-related applications such as the Reed-Solomon code, elliptic curve encryption/ decryption, is proposed. We utilized the VHDL language to verify the design methodology, and implemented the architecture on an FPGA chip. We suggested the n-bit lookup table method to obtain the throughput of 2m/n cycles, where m is the order of the division polynomial and n is the number of the most significant lookup-bits. By doing this, we extracted the advantages in achieving both high-throughput and less cost of the gate areaon the chip. A pilot FPGA chip was implemented with the case of m=4, n=2. We successfully utilized the Altera's EP20K30ETC144-1 to exhibit the maximum operating clock frequency of 77 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.6 s.249
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• pp.505-513
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• 2006

The pressure drop characteristics in a rotating two-pass duct with rib turbulators are investigated in the present study. Three ducts of different aspect ratios (W/H=0.5, 1.0 and 2.0) are employed with a fixed hydraulic diameter ($D_h$) of 26.7 mm. $90^{\circ}$-rib turbulators with $1.5mm{\times}1.5mm$ cross-section are attached on the leading and trailing surfaces. The pitch-to-rib height ratio (p/e) is 1.0. The distance between the tip of the divider and the outer wall of the duct is 1.0 W. The thickness of divider wall is 6.0 mm o. 0.225 $D_h$. The Reynolds number (Re) based on the hydraulic diameter is kept constant at 10,000 and the .elation number (Ro) is varied from 0.0 to 0.2. As duct aspect ratio increases, high friction factor ratios show in overall regions. The reason is that the rib height-to-duct height ratio (e/H) increases, but the divider wall thickness-to-duct width ($t_d/W$) decreases. The rotation of duct produces pressure drop discrepancy between the leading and trailing surfaces. However, the pressure drop discrepancy of the high duct aspect ratio (AR=2.0) is smaller than that of the low duct aspect ratio (AR=0.5) due to the decrement of duct hight (H).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.5
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• pp.694-700
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• 1999

In this paper, we studied the design of power divider using the slow-wave effect of Photonic Bandgap structure, which is etched on the ground plane. The proposed PBG structure can provides the changing of the characteristic impedance of the transmission line and the group delay velocity characteristic. Therefore we can make wider width than the width of conventional transmission line and decrease the length of transmission line. We presented the application for power divider using the characteristic impedance and electrical length extracted from scattering parameter. As adding proposed defect units, the effect of defect is studied. The experimental results show good agreements with the simulated results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.431-440
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• 2012

In this paper, new beam-forming array antenna is proposed. The proposed beam-forming array antenna has control ability for beam-direction/width by employing low loss reconfigurable power divide and three-dimensional array structure. The reconfigurable power divider is key idea in the proposed antenna, because it has reconfigurable RF power distribution ability to each antenna. And, for research and verification of the proposed antenna, 3-dimensional beam-forming array antenna is implemented, and the experimental results show that the proposed antenna has various radiation modes from 1:1 to 1:N by adjusting RF power distribution.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.2
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• pp.41-51
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• 2004

In this paper, the beam steering dipole phased array antenna systems for IMT-2000 base station have been designed. The designed beam steering dipole phased array antenna systems are constituted by the antenna part and the beam steering control system part. The antenna part is designed by the proposed flat dipole for the broadband characteristics, and the 8${\times}$8 dipole array antenna is constructed by the proposed flat dipole for the directional radiation pattern. Besides the vertical power divider is designed for the vertical power distribution. The beam steering control system part is designed the horizontal power divider for the horizontal power distribution, the 4-bit phase shifters and the driving circuit of phase shifters for the horizontal beam tilting. In order to evaluate a performance of the designed antenna systems, they were fabricated and the radiation characteristics were measured. From the measured results, we found that the horizontal beams were tilted by the each control signals, and the measured radiation characteristics showed good agreement with the design goals.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.8
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• pp.24-32
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• 2000

In this paper, we have designed and fabricated a new type power divider to be efficient to a size and electrical performance by folding each quarter-wavelength 70.7 Ω section into a tightly-coupled "meander-line" and inserting a slit. In this type, because of coupling, the electrical phase of quarter -wavelength line and the performance change. For this reason, with the inductive slit and the tuning of quarter-wavelength line length, we have compensated for those. The inductance value of the inserted slit is decided by its width and depth, therefore, we could improve the electrical performance through optimization of inductance. Input and output return losses of the designed power divider were -34.2 dB, -34.3 dB respectively, and isolation was -36.7 dB at 1.75 GHz. Besides, a new design approach reduced occupied substrate area by 3:1 approximately.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.80-85
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• 2003

This paper proposes Galois Field Arithmetic Unit(GFAU) whose structure does addition, multiplication and division in GF(2m). GFAU can execute maximum two additions, or two multiplications, or one addition and one multiplication. The base architecture of this GFAU is a divider based on modified Euclid's algorithm. The divider was modified to enable multiplication and addition, and the modified divider with the control logic became GFAU. The GFAU for GF(2193) was implemented with Verilog HDL with top-down methodology, and it was improved and verified by a cycle-based simulator written in C-language. The verified model was synthesized with Samsung 0.35um, 3.3V CMOS standard cell library, and it operates at 104.7MHz in the worst case of 3.0V, 85$^{\circ}C$, and it has about 25,889 gates.