• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.210-220
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• 2008

We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-to-digital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits. We note reader that this paper is not a new contribution, but a review in which we highlight the common theme from our published works [1-3]. We published a similar paper [4], which, however, used only two examples from [1] and [2]. With the newly added content from [3] in the list of our examples, the present paper offers an expanded scope.

• Journal of Power Electronics
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• v.13 no.3
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• pp.419-428
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• 2013

The modular multilevel cascade converter (MMCC) is a new family of multilevel power converters with modular realization and a cascaded pattern for submodules. The MMCC family can be classified by basic configurations and submodule types. One member of this family, the Hexverter, is configured as Double-Delta Full-Bridge (DDFB). It is a novel multilevel AC/AC converter with direct power conversion and comparatively fewer required components. It is appropriate for connecting two three-phase systems with different frequencies and driving an AC motor directly from a utility grid. This paper presents the dq model of a Hexverter with both of its AC systems by state-space representation, which then simplifies the continuous time-varying model into a periodic discrete time-invariant one. Then a generalized multivariable optimal control strategy for regulating the Hexverter's independent currents is developed. The resulting control structure can be adapted to other MMCCs and is flexible enough to include other control criterion while guaranteeing the original controller performance. The modeling method and control design are verified by simulation results.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2849-2852
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• 1999

This paper describes the fuzzy PD controller using simplified indirect inference method. First, the fuzzy PD controller is derived from the conventional continuous time linear PD controller. Then the fuzzification, control-rule base, and defuzzification using SIIM in the design of the fuzzy controller are discussed in detail. The resulting controller is a discrete time fuzzy version of the conventional PD controller. which has the same linear structure. but are nonlinear functions of the input signals. The proposed controller enhances the self-tuning control capability. particularly when the process to be controlled is nonlinear. As the SIIM is applied, the fuzzy Inference results can be calculated with splitting fuzzy variables into each action component and are determined as the functional form of corresponding variables. So the Proposed method has the capability of the high speed inference and extending the fuzzy input variables easily. Computer simulation results have demonstrated the superior to the control Performance of the one Proposed by D. Misir et at. Final)y. we simulated the contour control of the X-Y tables with direct control strategies using the proposed fuzzy PD controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.49-60
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• 2002

A systematic design approach for Power distribution network (PDN) is presented aiming at applications to DRAM module designs. Three main stages are comprised in this design approach: modeling and simulation of a PDN based on a two-dimensional transmission line structure employing a partial element equivalent circuit (PEEC); verification of the simulation results through comparison to measured values; and design space scanning with PDN parameters. Impedance characteristics for do-coupling capacitors are analyzed to devise an effective way to stabilize power and ground plane Performance within a target level of disturbances. Self-impedance and transfer-impedance are studied in terms of distance between circuit features and the size of do-coupling capacitors. A simple equation has been derived to find the do-coupling capacitance values yielding impedance lower than design target, and thereby reducing the overall computation time. The effectiveness of the design methodology has been demonstrated using a DRAM module with discrete do-coupling capacitors and a strip structure.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.211-216
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• 2012

Control Theory for continuous-time system has been well developed. Due to the development of computer technology, digital control scheme are employed in many areas. When delays are in control systems, it is hard to control the system efficiently. Delays by controller-to-actuator and sensor-to-controller deteriorate control performance and could possibly destabilize the overall system. In this paper, a new approximated discretization method and digital design for control systems with multiple state, input and output delays and a generalized bilinear transformation method with a tunable parameter are also provided, which can re-transform the integer time-delayed discrete-time model to its continuous-time model. Illustrative example is given to demonstrate the effectiveness of the developed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.297-305
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• 2007

In the paper, a Motion JPEG2000 coder which has been set as the standard for image compression by the Digital Cinema Initiatives (DCI), an organization composed of major movie studios was implemented into a target FPGA. The DWT (Discrete Wavelet Transform) based on lifting and the Tier 1 of EBCOT (Embedded Block Coding with Optimized Truncation) which are major functional modules of the JPEG2000 were setup with dedicated hardware. The Tier 2 process was implemented in software. For digital cinema the tile-size was set to support $1024\times1024$ pixels. To ensure the real-time operations, three entropy encoders were used. When Verilog-HDL was used for hardware, resources of 32,470 LEs in Altera's Stratix EP1S80 were used, and the hardware worked stably at the frequency of 150Mhz.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.161-167
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• 2017

Recently, small radar has been reduced in size and power consumption to cope with various operating environments. It also requires the development of a small millimeter wave radar with high range resolution to disable the system of target with a single strike. In this paper, we design and implement a signal processor that can be used in small millimeter wave radar. The signal processor for the small millmeter wave radar is designed with a digital IF(Intermediate Frequency) receiver and DFT(Discrete Fourier Transform) module capable of real time FFT operation for miniaturization and low power consumption. Also it was to leverage the FPGA(Field Programmable Gate Array) and DAC(Digital Analog Converter) as a means for correcting the distortion of signals that can occur in the receive path of the small millimeter wave radar to create a RF signal that is used by the system. Finally, we verified the signal processor presented through performance test

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.27-33
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• 1984

This paper is an experimental gaudy on the digital hardware implementation of the R2-MF Receiver for 32 channel configurations used in signalling systems between ESS. There are many methods to detect MF signal by DSP techniques, but the requirement for MF detection needs not sharp frequency response, needs only decision about some specific frequencies exist or not at discrete frequency sampling points. The hardware used to implement this algorithm is Am 2900 series "bit-slice microprocessor" chips based on the microprogramming techniques for real time signal processing. And we used the additional Z-80A processor chips for the system control and the decision about which is the right MF signal from the detected MF spectrums. Hence we could enhance the flexibilities of the hardware and the software, this leads that this system is well suits for signalling systems used in TDM ESS.n TDM ESS.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.11
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• pp.5537-5555
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• 2017

Having the characteristics of unlinkability, anonymity, and unforgeability, blind signatures are widely used for privacy-related applications such as electronic cash, electronic voting and electronic auction systems where to maintain the anonymity of the participants. Among these applications, the blinded message is needed for a certain purpose by which users delegate signing operation and communicate with each other in a trusted manner. This application leads to the need of proxy blind signature schemes. Proxy blind signature is an important type of cryptographic primitive to realize the properties of both blind signature and proxy signature. Over the past years, many proxy blind signature algorithms have been adopted to fulfill such task based on the discrete logarithm problem (DLP) and the elliptic curve discrete log problem (ECDLP), and most of the existing studies mainly aim to provide effective models to satisfy the security requirements concerning a single blinded message. Unlike many previous works, the proposed scheme applies the signcryption paradigm to the proxy blind signature technology for handling multiple blinded messages at a time based on elliptic curve cryptography (ECC). This innovative method thus has a higher level of security to achieve the security goals of both blind signature and proxy signature. Moreover, the evaluation results show that this proposed protocol is more efficient, consuming low communication overhead while increasing the volume of digital messages compared to the performance from other solutions. Due to these features, this design is able to be implemented in small low-power intelligent devices and very suitable and easily adoptable for e-system applications in pervasive mobile computing environment.

• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.81-91
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• 1994

A DCT map and new cldebook design algorithm based on a two-dimension discrete cosine transform (2D-DCT) is presented for coder of image vector quantizer. We divide the image into smaller subblocks, then, using 2D DCT, separate it into blocks which are hard to code but it bears most of the visual information and easy to code but little visual information, and DCT map is made. According to this map, the significant features of training image are extracted by using the 2D DCT. A codebook is generated by partitioning the training set into a binary tree based on tree-structure. Each training vector at a nonterminal node of the binary tree is directed to one of the two descendants by comparing a single feature associated with that node to a threshold. Compared with the pairwise neighbor (PPN) and classified VQ(CVQ) algorithm, about 'Lenna' and 'Boat' image, the new algorithm results in a reduction in computation time and shows better picture quality with 0.45 dB and 0.33dB differences as to PNN, 0.05dB and 0.1dB differences as to CVQ respectively.