Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Impedance Calculation of Power Distribution Networks for High-Speed DRAM Module Design

고속DRAM모듈 설계에 대한 전원평면의 임피던스계산

  • Lee, Dong-Ju (Chungbuk National University) ;
  • Younggap You (Dept. of Computer and Communication Eng. Chungbuk National University)
  • Published : 2002.03.01
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Abstract

A systematic design approach for Power distribution network (PDN) is presented aiming at applications to DRAM module designs. Three main stages are comprised in this design approach: modeling and simulation of a PDN based on a two-dimensional transmission line structure employing a partial element equivalent circuit (PEEC); verification of the simulation results through comparison to measured values; and design space scanning with PDN parameters. Impedance characteristics for do-coupling capacitors are analyzed to devise an effective way to stabilize power and ground plane Performance within a target level of disturbances. Self-impedance and transfer-impedance are studied in terms of distance between circuit features and the size of do-coupling capacitors. A simple equation has been derived to find the do-coupling capacitance values yielding impedance lower than design target, and thereby reducing the overall computation time. The effectiveness of the design methodology has been demonstrated using a DRAM module with discrete do-coupling capacitors and a strip structure.

본 논문에서는 DRAM 모듈의 전원 평면에 대한 효과적인 설계 방법을 제시하였고 그 방법은 다음과 같이 세 단계로 구성되어 있다. 1) PEEC 등가회로를 이용한 2D 전송선 구조로 전원평면의 모델링 및 해석. 2) 측정값 비교를 통한 해석 결과 검증. 3) 전원 평면의 물리적 파라미터를 이용한 설계 가이드 제시. 제시한 내용을 바탕으로 하여 DRAM 모듈에서 전원 및 접지평면 성능을 안정화를 이루기 위한 효과적인 De-coupling 커패시터의 용량과 개수를 결정하는 방법을 기술하였다 이 설계 방법론은 스트립 구조 및 do-coupling 커패시터를 갖는 DRAM 모듈에서 효과적으로 사용할 수 있다.

Keywords

References

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