• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.255-258
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• 1999

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.565-568
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• 2003

The conventional analog-based firing circuit can be implemented by comparing a linearly decreasing periodic sawtooth waveform synchronized to the ac line, with a voltage corresponding to the desired converter delay angle. This circuit requires a large number of components (resistance and capacitor) and careful adjustment of the synchronization circuity In this paper a novel firing circuit is proposed for thyristor switch is elements. The proposed circuit is implemented on the basis of the analog cosine method using FPGA and microprocessor.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2001.05a
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• pp.166-171
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• 2001

A digital seismic data acquisition and processing system using a PC has been developed in order to replace the analog data acquisition system of shallow marine seismic survey. An A/D converter that has 12bits of resolution and 225KHz of conversion rate was ued to acquire data, and a data acquisition software was developed as a Windows program which provides convenience of use. Raw data acquired at field has been saved to the hard-disk simultaneously. The signal to noise ratio, vertical and horizontal resolution could be improved by a digital data processing of the raw data. The digital processing of the raw data includss gain recovery, filtering, deconvolution, and muting. With the prediction deconvolution algorithm multiple reflections appearing on the shallow marine seismic section could be removed successfully.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.31-35
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• 2018

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC (digital-to-analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12b operation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The proposed SAR ADC is designed with a $0.18{\mu}m$ CMOS process. The simulation results show that the SNDR of the SAR ADC without the noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dB improvement in SNDR with this noise shaping technique. The power consumption is $73.8{\mu}W$ and the FoM (figure-of-merit) is 5.2fJ/conversion-step.

• Journal of Radiation Protection and Research
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• v.12 no.1
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• pp.12-25
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• 1987

A basic multichannel analyser (MCA) system have been designed and constructed with the successive approximation type ADC (Analog to Digital Converter). Linear Gate, window, and palse stretcher consist of mainly linear and logic IC's, and are properly combined together to achieve short dead time and good linearity of the system. ADC 1211 (analysing time: $120{\mu}sec$) and S-RAM (static random acess memory) 6264 are used in ADC module. Two 6264 memories are connected in parallel in order to-provide enough counting capacity ($2^{16}-1$). Interfaced microcomputer Apple II controls this system and analizes the counted data. The system is tested by input pulses between 0V to 10V from oscillator.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3201-3204
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• 2000

In general, analog tester or strip chart recorder have been used to measure the corrosion potential of structures such as gas pipelines, oil pipelines, hot water pipelines, power cables etc. Recently, automatic digital data logger substitutes for these manual equipment because using these manual equipments are tedious and time consuming. However, digital data logger also has a shortcoming, that is, short measuring time because of the short lifetime of batteries. Therefore, we developed a long lifetime and low power loss battery taking advantage of galvanic series. In this paper, the results of development for power generator using two metals and DC/DC converter in order to obtain enough voltage for the operation of digital data logger. DC/DC converter operates with 0.5[V]. Its output voltage is 3.5[V] and output current is from 60[mAh] to 1,200[mAh].

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.371-374
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• 2013

In this paper, a sensor node circuit using solar energy harvesting is proposed. PMU(Power Management Unit) manages the energy converted from a solar cell. In order to supply a constant voltage to the sensor node, an LDO (Low Drop Out Regulator) is used. The LDO drives a temperature sensor and a SAR ADC(Successive Approximate Register Analog-to-Digital Converter). The circuit has been designed in 0.35um CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.43-50
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• 2007

In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.5
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• pp.1-9
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• 1981

Experimental results on a 4-bit charge-coupled A/D converter are described. Major operations in the successive approximation algorithm are implemented in a monolithic chip, CCADC, which was fabricated usir p-channel CCD technology, with its die size of 4,200 mil2 Typical operating frequency range has been found out to be from 500Hz to 200kHz. In that frequency range, no missing code has been found in the whole signal range of 2.4 volts for ramp signal slewing at 1 LSB/(sampling time). A discussion is made on several layout techniques to conserve the nominal binary ratio of (8:4:2:1) among the areas of four adjacent potential wells (M wells), whose charge storing capacities correspond to each bit magnitude - 3.6 pC, 1.8 pC, 0.9 pC, and 0.45 pC nominal in the order of MSB to the LSB. The effect of 'dump slot', which is responsible for the excessive nonlinearity (2$\frac{1}{2}$LSB) in the A/D converter, is explained. A novel input scheme called 'slot zero insertion' to circumvent the deleterious effects of the dump slot is described with the experimental results.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1145-1152
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• 2019

In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.