• ETRI Journal
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• 제33권6호
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• 한국해양공학회지
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• 제24권1호
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• pp.166-171
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• 2010

In this paper, the front-end of a digital receiver with a 25 kHz carrier frequency, 5 kHz symbol rate, and any excess-bandwidth is designed using two basic facts. The first is known as the uniform sampling theorem, which states that the sampled sequence might not suffer from aliasing even if its sampling rate is lower than the Nyquist sampling rate if the analog signal is a bandpass one. The other fact is that if the sampling rate is 4 times the center frequency of the sampled sequence, the front-end processing complexity can be dramatically reduced due to the half of the sampled sequence to be multiplied by zero in the demixing process. Furthermore, the designed front-end is simplified by introducing sub-filters and sub-sampling sequences. The designed front-end is composed of an A/D converter, which takes samples of a bandpass filtered signal at a 20 kHz rate; a serial-to-parallel converter, which converts a sampled bandpass sequence to 4 parallel sub-sample sequences; 4 sub-filter blocks, which act as a frequency shifter and lowpass filter for a complex sequence; 4 synchronized switches; and 2 adders. The designed front-end dramatically reduces the computational complexity by more than 50% for frequency shifting and lowpass filtering operations since a conventional front-end requires a frequency shifting and two lowpass filtering operations to get one lowpass complex sample, while the proposed front-end requires only four filtering operation to get four lowpass complex samples, which is equivalent to one filtering operation for one sample.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.193-193
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• 2008

Wearable and ubiquitous micro systems will be greatly growing and their related devices should be self-powered in order to avoid the replacement of finite power sources, for example, by scavenging energy from the environment. With ever reducing power requirements of both analog and digital circuits, power scavenging approaches are becoming increasingly realistic. One approach is to drive an electromechanical converter from ambient motion or vibration. Vibration-driven generators based on electromagnetic, electrostatic and piezoelectric technologies have been demonstrated. Among various generator types proposed so far, piezoelectric generator possesses considerable potential in micro system. To overcome low mechanical-to-electric energy conversion, the piezoelectric device should activate in resonance mode in response to external vibration. Normally, the external vibration excretes at low frequency ranging 0.1 to 200 Hz, whereas the resonant frequencies of the devices are fixed as constant. Therefore, keeping their resonant mode in varying external vibration can be one of important points in enhancing the conversion efficiency. We investigated the possibility of use of multi-bender type piezoelectric devices. To match the external vibration frequency with the device resonant frequency, the various devices with different resonant frequency were chosen.

• 전기학회논문지
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• 제65권3호
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• pp.487-492
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• 2016

In this paper, a device for analyzing the pressure distribution during walking was produced by using the pressure sensor on the heel. This device was limited to a frequency band by using the 1st low-pass filter. And an algorithm to analyze the value of the quantity to pressure using a analog to digital converter. It is used by using the threshold voltage of pressure sensor, it is suggested the algorithm. The algorithm is detected the peak which is exceeded the threshold voltage. and thus in accordance, it is detected the number of steps. And the calorie consumption were detected by using it. Also it used an MCU and Bluetooth. And by confirming the data at the LCD of the other MCU, it was to reduce the size of the device. According to this algorithm, it has the advantage that there is no restriction on the activity than when using an imaging device and it is inexpensive than other sensors such as an acceleration sensor or a gyro and it is easy to handle.

• IEIE Transactions on Smart Processing and Computing
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• 제4권4호
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• 한국전자파학회논문지
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• 제19권11호
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• pp.1272-1280
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• 2008

본 논문에서는 빠른 천이 시간 및 고해상도 특성을 동시에 만족하기 위해 주로 사용되는 DDS Driven PLL 구조 주파수 합성기의 위상 잡음 분석을 위한 모델링 방안을 제안하였다. 기준 주파수 발진기(reference oscillator) 및 전압 제어 발진기(VCO: Voltage Controlled Oscillator)는 Leeson 모델을 적용하여 측정 데이터를 근사하는 방법을 사용하였고, DDS 칩의 위상 잡음원은 DAC(Digital to Analog Converter) 동작에 근사하여 모델링하였다. PLL의 위상 잡음은 디지털 분주기의 위상 잡음원으로 근사하여 모델링하였으며, 특히 저역 통과 필터(low pass filter)의 각 소자들의 위상 잡음은 전압 제어 발진기의 위상 잡음과 함께 고려하는 방법을 제안하였다. 모델링된 각 잡음 원들을 선형 시스템 영역에서 중첩의 원리를 이용하여 분석함으로써 주파수 합성기 출력의 위상잡음 분포를 예측하였고, 그 결과를 제작된 주파수 합성기의 측정 결과와 비교 평가하였다.

• 한국전자파학회논문지
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• 제20권1호
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• pp.52-59
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• 2009

현대의 레이더는 큰 클러터 환경에서 동작하기 위해 넓은 동적 영역을 요구한다. ADC(Analog-to-Digital Converter)가 발생시키는 스퓨리어스(spurious) 신호는 넓은 동적 영역을 구현하는데 걸림돌이 되고 있다. 본 논문에서는 ADC의 비선형 특성에 따른 능동 위상 배열 레이더 수신기의 이득을 분석하였다. ADC SFDR(Spurious Free Dynamic Range)은 시스템이 요구하는 동적 영역을 한정하고, 제한된 영역내에서 ADC SNR(Signal-to-Noise Ratio) 손실을 고려하여 ADC 동적 영역을 설정하였다. 그리고 계산된 능동 위상 배열 레이더의 안테나단 출력 잡음 전압과 ADC 입력 잡음 전압을 비교하여 수신기의 이득을 구하였다. 끝으로 응용 예제를 통한 전체적인 내용을 살펴보았다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1996년도 추계학술대회 논문집
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• pp.697-701
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• 1996

King Sejong's Striking water-clock which brought in use on the first of July in 1434 was mainly composed of timekeeping and time announcing parts signalling twelve double-hours, and five night-watches and night-watch-divisions automatically by means of ball-operating jackworks. The clock was arranged with dual timekeeping system, the one for a full day(twelve double-hours) and the other for five night-watches achieving twelve double-hours and one-hundred interval horary systems. The vessels were arrayed in inflow-type water-clock, a large reservoir on the highest story, a constant-level tank for supplying water to the measuring vessel evenly in the middle, and the lowest tank to receive water from the above constant-level tank. An indicator-rod on the float was raised upwards depending on the water-level increase to show timing scales and also to release small bronze balls from the ball-rack mechanisms implanted on the measuring vessel to signal timing intervals.

• 한국생산제조학회지
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• 제23권6호
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• pp.539-546
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• 2014

This paper describes an ultra-precision electronic clinometer, which is based on the capacitive-based fluid type, for detection of small inclination angles. The main parts of the clinometer low-noise electronics are two capacitance measurement circuits for converting the capacitances of the capacitors of the clinometer into voltages, and a differential amplifier for obtaining the difference of the capacitances, which is proportional to the input inclination angle. A 16 bit analog to digital (AD) converter is also embedded into the same circuit board, whose output is sent to a PC via RS-232C, for achieving a small noise level down to tens of ${\mu}v$. A compensation method, which is referred to as the delay time method for shortening the stabilization time of the sensor was also discussed. Experimental results have shown the possibility of achieving a measurement resolution of $0.0001^{\circ}$ as well as the quick measurement with the delay time method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.