• International Journal of Control, Automation, and Systems
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• v.4 no.1
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• pp.1-9
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• 2006

This paper presents the modeling and multivariable feedback control of a novel high-precision multi-dimensional positioning stage. This integrated 6-degree-of-freedom. (DOF) motion stage is levitated by three aerostatic bearings and actuated by 3 three-phase synchronous permanent-magnet planar motors (SPMPMs). It can generate all 6-DOF motions with only a single moving part. With the DQ decomposition theory, this positioning stage is modeled as a multi-input multi-output (MIMO) electromechanical system with six inputs (currents) and six outputs (displacements). To achieve high-precision positioning capability, discrete-time integrator-augmented linear-quadratic-regulator (LQR) and reduced-order linearquadratic-Gaussian (LQG) control methodologies are applied. Digital multivariable controllers are designed and implemented on the positioning system, and experimental results are also presented in this paper to demonstrate the stage's dynamic performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.26-35
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• 1997

This paper proposes a multi-bit $\Sigma\Delta$ modulator arcitecture which eliminates signal clipping problem. To avoid signal clipping, the output values of intgrators are monitored and modified by a reference value. This oepration is recorded as a digital code to restore actual signal value. Due to the digital code, the substraction of feedback value from the multi-bit quantizer can be calculated by a digital adder and this simplifies dAC operation making the accurate DAC of conventional multi-bit $\Sigma\Delta$ modulator scheme unnecessary. These features make N-th modulator can be implemented by sharing an integrator among N stages to decrease the required chip area. As an experimental example, a 4th order .sum..DELTA. modulator with oversampling ratio of 64 was simulated to show over 130 DB SNR at rail-to-rail input sinusoidal signal.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1131-1139
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• 1999

In this paper, we present a wide-bandwidth digital rebalance loop for a dynamically tuned gyroscope(DTG) based on {{{{ { H}_{2 } }}}} methodology. The operational principle and the importance of a rebalance loop are explaind, first. The augmented plant model is constructed, which includes a gyroscope model and an integrator. An {{{{ { H}_{ 2} }}}} based controller is designed for the augmented plant model. To verify the performance of the controller, a digital rebalance loop for a DTG is designed, fabricated and experimented. Through frequency response analyses and experiments using a real DTG, it is confirmed that the controller is more robustly stable and has a wider bandwidth compared with those of a conventional PID controller, contributing to the performance improvement of a DTG.

• Journal of IKEEE
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• v.19 no.1
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• pp.87-93
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• 2015

In this paper, a $145{\mu}W$, 87dB SNR, Low power 3rd order Sigma-Delta Modulator with Op-amp sharing is proposed. Conventional architecture with analog path and digital path is improved by adding a delayed feed -forward path for disadvantages that coefficient value of the first integrator is small. Proposed architecture has a larger coefficient value of the first integrator to remove the digital path. Power consumption of proposed architecture using op-amp sharing is lower than conventional architecture. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and sampling frequency 2.8224MHz shows SNR(Signal to Noise Ratio) of 87dB, the power consumption of $145{\mu}W$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of IKEEE
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• v.19 no.4
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• pp.479-485
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• 2015

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to $15.56{\mu}s/{\Omega}$ over the resistance deviation range of $0-200{\Omega}$ and its linearity error is less than ${\pm}0.02%$. Its temperature stability is less than $220ppm/^{\circ}C$ in the temperature range of $-25-85^{\circ}C$. Power dissipation of the converter is 60.2 mW.

• Journal of Power Electronics
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• v.5 no.2
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• pp.151-159
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• 2005

The errors generated from current measurement paths are inevitable, and they can be divided into two categories: offset error and scaling error. The current data including these errors cause periodic speed ripples which are one and two times the stator electrical frequency respectively. Since these undesirable ripples bring about harmful influences to motor driving systems, a compensation algorithm must be introduced to the control algorithm of the motor drive. In this paper, a new compensation algorithm is proposed. The signal of the integrator output of the d-axis current regulator is chosen and processed to compensate for the current measurement errors. Usually the d-axis current command is zero or constant to acquire the maximum torque or unity power factor in the ac drive system, and the output of the d-axis current regulator is nearly zero or constant as well. If the stator currents include the offset and scaling errors, the respective motor speed produces a ripple related to one and two times the stator electrical frequency, and the signal of the integrator output of the d-axis current regulator also produces the ripple as the motor speed does. The compensation of the current measurement errors is easily implemented to smooth the signal of the integrator output of the d-axis current regulator by subtracting the DC offset value or rescaling the gain of the hall sensor. Therefore, the proposed algorithm has several features: the robustness in the variation of the mechanical parameters, the application of the steady and transient state, the ease of implementation, and less computation time. The MATLAB simulation and experimental results are shown in order to verify the validity of the proposed current compensating algorithm.

• Journal of IKEEE
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• v.18 no.2
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• pp.192-197
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• 2014

In this paper, $3^{rd}$ SDM with FDPA(Feedback Delay Pass Addition) technique to improve the input range is proposed. Conventional architecture with $3^{rd}$ transfer function is just made as adding a digital delay path in $2^{nd}$ SDM architecture. But the input range is very small because feedback path into the first integrator is increased. But, proposed architecture change feedback path into the first integrator to the second integrator, so input range could be improved about 9dB. The $3^{rd}$ SC SDM with only one operational amplifier was implemented using double-sampling technique. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and audible sampling frequency 2.8224MHz show SNR(Signal to Noise Ratio) of 83.8dB, the power consumption of $700{\mu}W$ and Dynamic Range of 82.8dB.

• 전기의세계
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• v.26 no.3
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• pp.63-68
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• 1977

In this paper, the theory of pulse frequency modulated DC/DC power converter to obtain constant output voltage for all input voltage changes is discussed. The switch controller consisting of integrator and comparator determines the ON time of power switch-Thyristor-by the error between the load voltage and a load reference voltage. Resulting voltage and current waveforms have been studied theoretically in detail and verified experimentally for a resistive and inductive load condition. State equations for voltages and currents using binary logic variables are computed by digital computer. Comparison of these withe oscillograms obtained from an experimental model shows very close agreement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.