• Journal of Information Processing Systems
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• 제10권2호
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• pp.223-239
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• 2014

New IIR digital differintegrators (differentiator and integrator) with very minor absolute relative errors are presented in this paper. The digital integrator is designed by interpolating some of the existing integrators. The optimum value of the interpolation ratio is obtained through linear programming optimization. Subsequently, by modifying the transfer function of the proposed integrator appropriately, new digital differentiator is obtained. Simulation results demonstrate that the proposed differintegrator are a more accurate approximation of ideal ones, than the existing differintegrators. Furthermore, the proposed differentiator has been tested in an image processing application. Edges characterize boundaries and are, therefore, a problem of fundamental importance in image processing. For comparison purpose Prewitt, Sobel, Roberts, Canny, Laplacian of Gaussian (LOG), Zerocross operators were used and their results are displayed. The results of edge detection by some of the existing differentiators are also provided. The simulation results have shown the superiority of the proposed approach over existing ones.

• 대한전자공학회논문지
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• 제26권12호
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• pp.2046-2054
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• 1989

Improved algorithms are presented to design linear phase digital FIR filters with coefficients of +1,0,-1 only followed by a multiple integrator. It has been shown that the existing linear phase filter design concept for the single integrator(or, accumulator)case can be extended to the case of the multiple integrator. Linear phase conditions for the multiple integrators are summarized. Filter design methods with double or triple integrator are exploited in datail and its computer simulation results are presented to deduce the advantages of multiple integrator to the single integrator.

• 전자공학회논문지
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• 제54권1호
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• pp.26-32
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• 2017

본 논문에서는 설계 요구가 높고, 전력 소모가 높은 opamp를 이용하는 기존의 능동형 적분기를, 수동형 적분기로 대체하여 고속의 저전력, 고해상도 특성을 갖는 incremental delta-sigma ADC를 소개한다. 능동형 적분기에서 수동형 적분기로의 변환을 위해, 기존의 능동형 적분기의 특성을 분석하였다. 이를 바탕으로 opamp의 설계 요구를 낮추고, 더 나아가 opamp를 사용하지 않는 저전력의 수동형 적분기를 제안하였다. 65nm 공정을 이용하여 수동형 적분기로 구성된 1차 single-bit incremental delta-sigma ADC를 설계하였다. Transistor-level 시뮬레이션 결과, 이는 supply 전압이 1.2V인 상황에서 modulator만 0.6uW, digital filter를 포함한 ADC 전체에서 6.25uW를 소모하며 BW 22KHz, SNDR 71dB, dynamic range 74.6dB을 달성하였다.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.14-18
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• 1997

A design methodology of the analog current-mode and width programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by the 0.8$\mu\textrm{m}$ CMOS n-well single poly/double metal standard digital process. The integrator occupies the active chip area of 0.3$\textrm{mm}^2$. The experimental result illustrates a low power dissipation (1.0mW∼3.55 mW), 65dB of the dynamic range, and digitally and width programmability (10MHz∼30MHz) with an external digital 4 bit.

• 센서학회지
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• 제31권2호
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• pp.115-119
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• 2022

A readout circuit for a mercury-cadmium-telluride (MCT)-amplified mid-wave infrared (IR) photodetector was realized and applied to noncontact chemical agent detectors based on a quantum cascade laser (QCL). The QCL emitted 250 times for each wavelength in 0.2-㎛ steps from 8 to 12 ㎛ with a frequency of 100 kHz and duty ratio of 10%. Because of the nonconstant QCL emission power during on-duty, averaging the photodetector signals is essential. Averaging can be performed in digital back-end processing through a high-speed analog-to-digital converter (ADC) or in analog front-end processing through an integrator circuit. In addition, it should be considered that the 250 IR data points should be completely transferred to a PC during each wavelength tuning period of the QCL. To average and minimize the IR data, we designed a readout circuit using the analog front-end processing method. The proposed readout circuit consisted of a switched-capacitor integrator, voltage level shifter, relatively low-speed analog-to-digital converter, and micro-control unit. We confirmed that the MCT photodetector signal according to the QCL source can be accurately read and transferred to the PC without omissions.

• 한국음향학회지
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• 제16권3호
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• pp.106-113
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• 1997

본 논문에서는 저전압 아날로그-디지털 혼성모드 신호처리를 위한 3V CMOS 연속시간 완전균형 적분기가 설계되었다. 설계된 완전균형 적분기의 기본구조는 NMOS와 PMOS 트랜지스터를 이용한 상보형 회로이며, 이러한 상보형 회로는 적분기의 트랜스컨덕턴스를 증가시킬수 있는 장점이 있다. 그리고 트랜스컨덕턴스의 증가는 적분기의 단위이득 주파수, 폴 그리고 영점을 증가시킨다. 소신호해석과 SPICE 시뮬레이션을 통해 기존의 적분기들과 비교하여 이러한 개선점들을 증명하였다. 0.8 3V CMOS CMOS 공정 파라미터를 이용하여 완전균형 상보형 적분기의 응용회로로서 3차 능동 지역통과 필터를 설계하였다.

• 한국정보통신학회논문지
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• 제25권11호
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• pp.1619-1626
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• 2021

증분형 아날로그 디지털 변환기는 전통적인 델타 시그마 아날로그 디지털 컨버터와 달리 리셋 동작을 통한 입력과 출력의 1:1 매핑이 가능하며 이는 멀티플렉싱에 매우 용이하게 사용될 수 있다. 또한, 증분형 아날로그 디지털 변화기는 전통적인 델타 시그마 변환기에 비해 간단한 디지털 필터 설계가 가능하다. 따라서, 본 논문에서는 아날로그 디지털 컨버터 설계에 기본이 되는 딜레이가 있는 적분기와 딜레이가 없는 적분기의 시간 영역에서의 분석을 시작으로 2차 입력 피드 포워드, 확장된 카운팅, 2+1 매쉬, 2+2 매쉬 구조를 갖는 증분형 아날로그 디지털 변환기의 설계 방정식을 유도한다. 이를 통해 설계 이전에 증분형 아날로그 디지털 변환기의 성능을 예측할 수 있을 뿐만 아니라 각각의 아날로그 디지털 변화기에 적합한 디지털 필터를 설계할 수 있다. 또한, 아날로그 디지털 변환기의 정확도를 향상 시키기 위한 확장된 카운팅, MASH의 설계 기술들을 제안하였다.

• 전기학회논문지
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• 제62권7호
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• pp.891-897
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• 2013

The power system frequency plays an important role in monitoring and controlling the power system. The frequency can be measured through discrete Fourier transform (DFT) coefficients of its positive fundamental frequency. The accuracy of the frequency estimate is severely affected by noise in the power system signal and the leakage effect of the negative fundamental frequency in DFT. This paper proposes a DFT-based frequency estimation algorithm to cope with the noise as well as the leakage effect. In this algorithm, two suitable digital filters are introduced to reduce efficiently frequency estimate error due to the noise. These filters are designed to use a digital bandpass filter and a second-degree integrator. The effectiveness of the proposed algorithm in reduction of frequency estimate error is verified through simulations on noise, harmonics and frequency deviation.

• 대한전자공학회논문지
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• 제27권5호
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• pp.808-815
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• 1990

This paper treats with the design method for the single loop oversampled Sigma-Delta A/D converter with one delay and the digital integrator. Such an integrator was kgenerated by means of the bilinear transform of the analog integrator. The frequency spectrums of the quantizer and the decimator output signal are evaluated by FFT respectively. With the performance evaluation system, the values of SNR are obtained versus the input sinusoidal signal amplitude, frequency, the oversampling ratio, the DC-input level, the loop gain and the limitting value of the integrator. As compared with existing results, values of SNR versus the input signal amplitude and the oversampling ratio for the suggested system are about 6dB higher then previously reported results respectively. Furthermore, this approach achieves an about 60dB input dynamic range.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국제학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.530-533
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• 1993

This paper describes a new method of dynamic error compensation, using a digital convolution integrator and two digital low pass filters. In this method, the process of compensation consists of three steps. First, sampling and digitizing of input signal, second, removing the noise in sampled data by the low pass filter and third, making a convolution integral using the output data of low pass filters. This method showed a good experimental result of reducing dynamic error even if there was a slight noise in the input signal. As a result, the detecting time constant of resistance thermo-bulb was improved to about 1/10th.