초록
A design methodology of the analog current-mode and width programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by the 0.8$\mu\textrm{m}$ CMOS n-well single poly/double metal standard digital process. The integrator occupies the active chip area of 0.3$\textrm{mm}^2$. The experimental result illustrates a low power dissipation (1.0mW∼3.55 mW), 65dB of the dynamic range, and digitally and width programmability (10MHz∼30MHz) with an external digital 4 bit.
