• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.612-616
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• 2016

Gamma-ray must be detected and processed immedietely after generation of it in the circumstances where it exists. Software methology may be used to process randomly generated signals, but its memory size and processing time become large. By the way, the hardware circuit to detect randomly generated signals is generalized in industrial site, while those circuits are not able to answer to the cases whose amplitude are very small and also speed high. We researched and developed hardware based peak-hold circuit that is able to detect peaks of gamma-ray signals through direct reading out their values by ADC at the time of maximum reaching for the small amplitude and high speed signals, and proposed and estimated its results in this paper. This peak-hold circuit is adequate to use in the radiation circumstances in which the gamma-rays are heavy because its circuit can catch high speed signals efficiently without software signal processing supports.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.419-425
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• 2001

In land mobile communications, multipath fading is one of the key factors which affect the system performance. Some extensive studies have been carried out to improve the degraded performance under this fading channels. The PSAM channel compensation method using channel fading estimation is widely used and TCM is a combined coding and modulation technique that has been shown to provide significant coding gain without increasing the transmission bandwidth. In this paper, we analyze the performance of PSA-TC-8PSK which combines PSAM and TCM over frequency nonselective fading channels. To estimate channel fading, Wiener filter which minimizes error variance is used as compensation method and we analyze the affects on the system performance of the number of filter taps, period of the pilot symbol frame, and the Doppler frequency. In addition, we consider the symbol timing recovery circuit which can be implemented in the full-digital method and analyze the effects of symbol timing error on the system performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.51-55
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• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.668-670
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• 2011

The Next-generation IT technology has been evolving from single technique to another which has merged, converging characteristics. The government categorized the 5 essential technologies to secure competitiveness in designing system semiconductors as smart motor vehicle info-tainment platform, smart TV multimedia system, smart phone analog interface technique, smart convergence digital communication and RF techniques, and advanced power management for smart devices. Also, it designated smart phone, smart TV, smart motor vehicle, and smart pad as the key industries. Such core techniques will become the key technologies of semiconductor design to secure the competitiveness of the next generation smart devices and the techniques can be transferred to fab-less design companies. In this contribution, we analyze the issues and the problems of the smart phone analog and interface techniques.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.11
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• pp.2479-2485
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• 2013

In this paper, we present a design for solid-state radar SSPA with sequential bias. We apply to variable extension pulse generator to eliminate signal distortion which is caused by bias rising/falling delay of power amplifier. There is an optimum impedance matching circuit to have high efficiency of GaN-power device by measuring microwave characteristics through load-pull method. The designed SSPA is consisted of pre-amplifier, drive-amplifier and main-amplifier as a three stages to apply for X-Band solid-state radar. Thereby we made a 200W SSPA which has output pulse maximum power shows 53.67dBm and its average power is 52.85dBm. The optimum design of transceiver module for solid-state pulse compression radar which is presented in this dissertation, it can be available to miniaturize and to improve the radar performances through additional research for digital radar from now on.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.411-421
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• 2002

In this paper, we present a new survivor path memory management method and a dedicated hardware architecture for the design of high-speed Viterbi decoders in modern digital communication systems. In the proposed method, a novel use of k-starting node number deciding circuits enables to acheive the immediate traceback of the merged survivor path from which we can decode output bits, and results in smaller survivor path memory size and processing delay time than the previously known methods. Also, in the proposed method, the survivor path memory can be constructed with ease using a simple standard dual-ported memory since one read-pointer and one write-pointer, that are updated at the same rate, are required for managing the survivor path: the previously known algorithms require either complex k-ported memory structure or k-times faster read capability than write. With a moderate hardware cost for immediate traceback capability the proposed method is superior to the previously known methods for high-speed Viterbi decoding.