• Prospectives of Industrial Chemistry
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• v.23 no.2
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• pp.1-11
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• 2020

In this report, we summarize recent progress in the development of electrolyte-gated transistors (EGTs) for various printed electronics. EGTs, employing a high capacitance electrolyte as gate dielectric layer in transistors, exhibits increasing of drive current, lowering operation voltage, and new transistor architectures. While the use of electrolytes in electronics goes back to the early days of silicon transistors, the new printable, fast-responsive polymer electrolytes are expanding their range of applications from printable and flexible digital circuits to various neuromorphic devices. This report introduces the structure and operating mechanism of EGT and reviews key developments in electrolyte materials used in printed electronics. Additionally, we will look at various applications with EGTs that are currently underway.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.387-393
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• 1987

The introduction of a digiral subscriber loop transmission system necessitates an optimized line interface solution. To meet this objective an adaptive line equalizer has been developed. The equalizer can be compensated up to 42 dB line loss at 200KHz, and operated up to 3.2 Km transmission length (0.4 mm\ulcornercable)at a rate of 400Kb/s. This has been builted using a variable \ulcorner equalizer to compensate a frequency-attenuation characteristics of metallic cable, an AGC (automatic gain control) circuits with simple control algorithm, and various filters to minimize a transmission constraints over subscriber loop. The purpose of this paper is to present a short description of a design of the adaptive line equalizer with a summary of implementation results. Some design concepts and considerations which results in an implementation of the equalizer are also given.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.2
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• pp.325-328
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• 2022

A convolutional neural network(CNN) is widely used in the computer vision tasks, but its computing power requirement needs a design of a special circuit. Most of the computations in a CNN can be implemented efficiently in a digital circuit, but the SoftMax layer has operations unsuitable for circuit implementation, which are exponential and logarithmic functions. This paper proposes a new method to integrate the exponential and logarithmic tables of the conventional circuits into a single table. The proposed structure accesses a look-up table (LUT) only with a few maximum values, and the LUT has the result value directly. Our proposed method significantly reduces the space complexity of the SoftMax layer circuit implementation. But our resulting circuit is comparable to the original baseline with small degradation in precision.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.854-862
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• 1993

All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.11 no.1
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• pp.63-71
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• 2017

In this paper, a signal processing circuit for semi-implantable middle ear hearing device is designed using the TCBT which is recently proposed for a new middle ear transducer that can be implanted at round window of cochlea. The designed semi-implantable hearing device transmits digital sound signal from external device located at behind the ear to the internal device implanted under the skin using inductive coupling link methods with high efficiency. The coils and signal processing circuits are designed and implemented considering the total transmission and reception distance including skin thickness of temporal bone for the semi-implantable hearing device. And also, to improve the data transmission efficiency, the output circuits which can supply sufficient signal power is designed. In order to confirm operation of semi-implantable hearing device using inductive coupling link, the circuit analysis was performed using PSpice, and the performance was verified by implementing a signal processing board of an available size.

• The Transactions of the Korea Information Processing Society
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• v.4 no.5
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• pp.1371-1379
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• 1997

Undetectable faults in a digital circuit are faults that no input patterms can detect.Identifying these faults in test geferation process is very time- consuming especially for sequential circuits .In this paper we present a new algorithm to identify unedtectable faults in sequential cirouits .In the alorithm. we identify uninitializable fip-flops and then, faults that prevent intialization of the fkip-flops(FPIs)are identified, finally propagation path of the FPI is checked. Time complexity of this algorithm is porportional to the product of the number of flip flops with at lest a self loop and the number of gates in the circuit. Experiments were performed on the ISCAS89 benchmark ciruits to show the feadibility of the proposed algorithm.We could identify large amount of undetectable faults(up to 50% of the number of flip-flops)in circuits with uninitializable flip-flops. Consider-ing that most of the time in test generation is cinsumed in identifying undetecatable faults, performance of test generator can be improved by using this algorithm as a pre-processing of test generation.

• Journal of Engineering Education Research
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• v.6 no.1
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• pp.56-64
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• 2003

In this paper, we designed and implemented a client/server distributed environment and developed a web-based virtual laboratory system for electronic circuits. Since our virtual laboratory system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. The proposed virtual laboratory system is composed of four important components : Principle Classroom, Virtual Experiment Classroom, Evaluation Classroom and Overall Management System. Through our virtual laboratory, the learners will be capable of learning the concepts and theories related to electronic circuit experiments and how to operate the experimental equipments such as multimeters, function generators, digital oscilloscopes and DC power supplies. Also, every experimental activity occurred in our virtual laboratory is recorded on database and printed out on the preliminary report form. All of these can be achieved by the aid of the Management System. The database connectivity on the web is made by PHP and the virtual labol'atory environment is set up slightly differently for each learner. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.153-159
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• 1989

This paper describes the algorithms employed in the preprocessing stage of the timing simulator, TSIM1.0, which is based on the Waveform Relaxation Method (WRM) at the CELL-level. The preprocessing stage in TSIM1.0 (1)partitions a given circuit into DC connected blocks (DCB's) (2) forms strongly connected circuts (SCC's) and (3) orders CELL's Also, the efficient waveform management technique for the WRM is described, which allows the overwriting of the waveform management technique for the WRM is described. which allows the overwriting of the waveform information to save the storage requirements. With TSIM1.0, circuits containing up to 5000 MOSFET's can be analyzed within 1 hour computation time on the IBM PC/AT. The simulation results for several types of MOS digital circuits are given to verify the performance of TSIM1.0.