• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1210-1230
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• 1997

In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.110-120
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• 2016

A power-efficient neuromodulator is needed for implantable systems. In spite of their stimulation signal's simplicity of wave shape and waiting time of MCU(micro controller unit) much longer than execution time, there is no consideration for low-power design. In this paper, we propose a novel of low-power algorithm based on the characteristics of stimulation signals. Then, we designed and implement a neuromodulation software that we call NMS(neuro modulation simulation). In order to implement low-power algorithm, first, we analyze running time of every function in existing NMS. Then, we calculate execution time and waiting time for these functions. Subsequently, we estimate the transition time between active mode (AM) and low-power mode (LPM). By using these results, we redesign the architecture of NMS in the proposed low-power algorithm: a stimulation signal divided into a number of segments by using characteristics of the signal from which AM or LPM segments are defined for determining the MCU power reduces to turn off or not. Our experimental results indicate that NMS with low-power algorithm reducing current consumption of MCU by 76.31 percent compared to NMS without low-power algorithm.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.355-355
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• 2002

In this paper, we designed a FPU(floating point unit) that it is very important and requires of high density when digital audio is designed. Almost audio system must support the multi-channel and required for high quality. A floating point arithmetic function in MPEG-2 AAC that implemented by hardware is able to realtime decoding when DSP realization. The reason is that MPEG-2 AAC is compatible to the Audio field of MPEG-4 and afterwards. We designed a FPU by hardware to increase the speed of a floating point unit with much calculation part in the MPEG-2 AAC Decoder. A FPU is composed of a multiplier and an adder. A multiplier used the Radix-4 Booth algorithm and an adder adopted 1's complement method for speed up. A form of a floating point unit has 8bit of exponent part and 24bit of mantissa. It's compatible with the IEEE single precision format and adopted a pipeline architecture to increase the speed of a processor. All of sub blocks are based on ISO/IEC 13818-7 standard. The algorithm is tested by C language and the design does by use of VHDL(VHSIC Hardware Description Language). The maximum operation speed is 23.2MHz and the stable operation speed is 19MHz.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• International Journal of Advanced Culture Technology
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• v.10 no.1
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• pp.248-252
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• 2022

The environment refers to what is surrounded by something during human life. This environment is related to the way humans live, and presents various problems on how to perceive the surrounding environment and how the behaviors that constitute the environment support the elements necessary for human life. Humans have an interest in the supportability of the environment as the interrelationship increases as humans perceive and understand the environment and accept the factors supported by the environment. In space, human movement starts from one space to the next and exchanges stimuli and reactions with the environment until reaching a target point. These human movements start with subjective judgment and during gait movement, the spatial environment surrounding humans becomes a collection of information necessary for humans and gives stimulation. will do. In this process, in particular, humans move along the movement path through movement in space and go through displacement perception and psychological changes, and recognize a series of spatial continuity. An image of thinking is formed[1]. In this process, spatial experience is perceived through the process of filtering by the senses in the real space, and the result of cognition is added through the process of subjective change accompanied by memory and knowledge, resulting in human movement. As such, the spatial search behavior begins with a series of perceptual and cognitive behaviors that arise in the process of human beings trying to read meaning from objects in the environment. Here, cognition includes the psychological process of sorting out and judging what the information is in the process of reading the meaning of the external environment, conditions, and material composition, and perception is the process of accepting information as the first step. It can be said to be the cognitive ability to read the meaning of the environment given to humans. Therefore, if we can grasp the perception of space while moving and human behavior as a response to perception, it will be possible to predict how to grasp it from a human point of view in a space that does not exist. Modern people have the theme of reminiscing dog-friendly hotels for the healing of petloss syndrome, and this thesis attempts to approach the life of companions.

• Journal of the Korean Institute of Landscape Architecture
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• v.36 no.3
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• pp.63-74
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• 2008

With the awareness that Sinyeongwol Sipgyeong(ten scenic spots in Yeongwol) were designed too hastily and only for PR purposes after the change in the tourism environment, this paper indicates that most tourism and culture sources in Yeongwol are related to King Danjong, the sixth king of the Joseon Dynasty. This study proposes a 'Storytelling Plan' for the landscape content called 'Cultural Landscapes - Yeongwol Palgyeong(eight scenic spots in Yeongwol)' after reviewing types and content of Yeongwol Palgyeong through the halo effect of the well-known sad history of King Danjong and the cultural value of Yeongwol. The significance of the unity of the historic site and neighboring landscape is focused on by investigating the anaphoric relations between cultural landscape texts('Yeongwol Palgyeong') and historic content(the sad history of King Danjong). For this, the cultural lnddscape of Yeongwol has been framed and layered to make spatial texts. To emphasize the 'Telling' as well as the 'Story,' interesting episodes have been reviewed to discover a motive. To diversify the 'Telling' methods, absorptive landscape factors have been classified as 'Place,' 'Object' and 'Visual Point.' In addition the storytelling of Yeongwol Palgyeong was examined in consideration of the story and background of 'Yeongwol Palgyeong - Sad Story of King Danjong' and the interaction of a variety of cultural content by suggesting micro-content such as infotainment and edutainment as absorptive landscape factors. In order to make the storytelling plan available in practice as an alternative plan for Yeongwol Tourism, a visual point should be properly set to make the landscape look sufficiently dynamic. In addition, real landscape routes and narration scenarios should be prepared as well. Professional landscape interpreters who are well informed of the natural features of Yeongwol and the history of King Danjong should be brought into the project, and Internet and digital technology-based strategies should be developed.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.3
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• pp.240-247
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• 2001

Java is a promising runtime environment for embedded systems because it has many advantages such as platform independence, high security and support for multi-threading. One of the most famous Java run-time environments, Sun's ($PersonalJave^{TM}$) is based on Truffle architecture, which enables programmers to design various GUIs easily. For this reason, it has been ported to various embedded systems such as set-top boxes and personal digital assistants(PDA's). Basically, Truffle uses heavy-weight window managers such as Microsoft vVin32 API and X-Window. However, those window managers are not adequate for embedded systems because they require a large amount of memory and disk space. To come up with the requirements of embedded systems, we adopt Microwindows as the platform graphic system for Personal] ava A WT onto Embedded Linux. Although Microwindows is a light-weight window manager, it provides as powerful API as traditional window managers. Because Microwindows does not require any support from other graphics systems, it can be easily ported to various platforms. In addition, it is an open source code software. Therefore, we can easily modify and extend it as needed. In this paper, we implement Personal]ava A WT using Microwindows on embedded Linux and prove the efficiency of our approach.