• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.9
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• pp.4467-4486
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• 2016

Discrete cosine transform (DCT) based JPEG standard significantly improves the coding efficiency of image compression, but it is unacceptable event in serious blocking artifacts at low bit rate and low efficiency of high-definition image. In the light of all phase digital filtering theory, this paper proposes a novel transform based on discrete sine transform (DST), which is called all phase discrete sine biorthogonal transform (APDSBT). Applying APDSBT to JPEG scheme, the blocking artifacts are reduced significantly. The reconstructed image of APDSBT-JPEG is better than that of DCT-JPEG in terms of objective quality and subjective effect. For improving the efficiency of JPEG coding, the structure of JPEG is analyzed. We analyze key factors in design and evaluation of JPEG compression on the massive parallel graphics processing units (GPUs) using the compute unified device architecture (CUDA) programming model. Experimental results show that the maximum speedup ratio of parallel algorithm of APDSBT-JPEG can reach more than 100 times with a very low version GPU. Some new parallel strategies are illustrated in this paper for improving the performance of parallel algorithm. With the optimal strategy, the efficiency can be improved over 10%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Structural Engineering and Mechanics
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• v.63 no.1
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• pp.37-46
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• 2017

This paper is concerned with the numerical study on the resonance response of a rigid spar-type floating platform in coupled heave and pitch motion. Spar-type floating platforms, widely used for supporting the offshore structures, offer an economic advantage but those exhibit the dynamically high sensitivity to external excitations due to their shape at the same time. Hence, the investigation of their dynamic responses, particularly at resonance, is prerequisite for the design of spar-type floating platforms which secure the dynamic stability. Spar-type floating platform in 2-D surface wave is assumed to be a rigid body having 2-DOFs, and its coupled dynamic equations are analytically derived using the geometric and kinematic relations. The motion-variance of the metacentric height and the moment of inertia of floating platform are taken into consideration, and the hydrodynamic interaction between the wave and platform motions is reflected into the hydrodynamic force and moment and the frequency-dependent added masses. The coupled nonlinear equations governing the heave and pitch motions are solved by the RK4 method, and the frequency responses are obtained by the digital Fourier transform. Through the numerical experiments to the wave frequency, the resonance responses and the coupling in resonance between heave and pitch motions are investigated in time and frequency domains.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.106-113
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• 1997

A 3V CMOS continuous-time fully-balanced integrator for low-voltage analog-digital mixed-mode signal processing is designed in this paper. The basic architecture of the designed fully-balanced integrator is complementary circuit which is composed of NMOS and PMOS transistor. And this complementary circuit can extend transconductance of an integrator. So. the unity gain frequency, pole and zero of integrator are increased by the extended transconductance. The SPICE simulation and small signal analysis results show that the UGF, pole and zero of the integrator is increased larger than those of the compared integrtors. The three-pole active low-pass filter is designed as a application circuit of the fully-balanced integrator, using 0.83V CMOS processing parameter.

• Journal of Korea Multimedia Society
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• v.16 no.10
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• pp.1204-1213
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• 2013

With the development of digital satellite communication technology and the widespread use of smart devices, the demand for data communication in the maritime ship has increased. Recently, the communication between the maritime ship and the land is based on Inmarsat satellite service. The Inmarsat provides telephone, fax, data and telex service etc. However, since the satellite is payper-seconds billing service, the transmission of whole web contents to the maritime ship through the satellite causes high cost. In this paper, we propose web browsing system architecture that reduces the data traffic on the satellite link and retransmits the content selectively in order to solve these problems.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.149-158
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• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.1
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• pp.5-14
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• 2002

This study presents a solution to control a Permanent Magnet Synchronous Motor without sensors based on the superposition principle. Because the proposed method of sensorless theory is very simple to compute the estimated angle, computing time to estimate the angle is shorter than other sensorless method. The use of this system yields enhanced operations, fewer system components, lower system cost, energy efficient control system design and increased efficiency. The performance of a sensorless architecture allows an intelligent approach to reduce the complete system costs of the digital motion control applications using cheaper electrical motors without sensors. This paper deals with an overview of sensorless solutions in PMSM control applications whereby the focus will be on the new controller without sensors and its applications.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.1
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• pp.1-7
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• 2003

A recent technology trends in synthetic aperture radar(SAR) requires the ultra high resolution performance in detecting and precisely identifying the targets. In this paper, as a technique for enhancing the radar range resolution, the wideband chirp connection algorithm is presented by stitching the several chirp modules with unit bandwidth based on the linear frequency modulated chirp signal waveform. The principles of the digital chirp signal generation and its architecture for implementation is briefly described, and the wideband chirp signal generator, modulator, and demodulator are designed. The performance analysis for the presented algorithm is given with the simulation results.

• 전자공학회논문지 IE
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• v.43 no.3
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• pp.6-12
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• 2006

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glitch-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in $0.35{\mu}m$ Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification and the prototype error between DNL and INL is less than $\pm$0.09LSB respectively. Also, the manufactured DAC chip was analyzed the cause of error operation and proposed the field considerations for chip test.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.2
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• pp.213-221
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• 2011

Avionics system tends to be designed to have the integrated architecture, and it is getting difficult and complex to verify the flight-critical function because of sophisticated structure. In Korean Utility Helicopter, mission computer acts as the MUX Bus Controller to handle the data from both communication, identification, mission/display and survivability equipment inside Mission Equipment Package and aircraft subsystems such as fuel system and electrical system while it is interfacing with Automatic Flight Control System and Full-Authority Digital Engine Control via ARINC-429 bus. The Flight Displays which is classified as flight-critical function in aircraft is implemented on Primary Flight Display after mission computer processes data from AFCS in order to generate graphics. This paper defines the flight-critical function implemented in mission computer for KUH, and presents the static and dynamic test procedures which is performed on System Integration Laboratory along with Playback Recorder prior to flight test.