• Journal of the Korean Society for information Management
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• v.21 no.2
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• pp.69-87
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• 2004

This study examines basic concepts and characteristics of QuestionPoint, the typical model of Collaborative Digital Reference Service and Global Reference Network, and analyzes the case of Question포인트 service at Korea Institute of Science and Technology Information where the service is initiated first time in Korea by developing Korean interface. 114 reference questions were analyzed, and questionnaires were sent to 63 service users to find out their overall attitudes and degree of satisfaction. Some suggestions were made by discussing the necessity of the enhancement of CDRS and mutual cooperation among Korean libraries.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.3
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• pp.615-622
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• 2007

In general, Harris detector is commonly used for finding salient points in watermarking systems using feature points. Harris detector is a kind of combined comer and edge detector which is based on neighboring image data distribution, therefore it has some limitation to find accurate salient points after watermark embedding or any kinds of digital attacks. In this paper, we have used cross reference points which use not data distribution but geometrical structure of a normalized image in order to avoid pointing error caused by the distortion of image data. After normalization, we find cross reference points and take inverse normalization of these points. Next, we construct a group of triangles using tessellation with inversely normalized cross reference points. The watermarks are affine transformed and transformed-watermarks are embedded into not normalized image but original one. Only locations of watermarks are determined on the normalized image. Therefore, we can reduce data loss of watermark which is caused by inverse normalization. As a result, we can detect watermarks with high correlation after several digital attacks.

• Journal of the Korean Society for information Management
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• v.22 no.1 s.55
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• pp.249-265
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• 2005

This paper outlines the concept of real time reference service(RTRS). Then, it analyzes real time reference service in the 13 libraries for effective reference service. As a result, the most used software was AOL instant Messenger, followed by Conference Room from WebMaster, and LivePerson. Hours of service was generally same as reference desk hours. The users were Students. faculty, staff, and alumni, This study also demonstrated how the RTRS in LC works. The results showed that real time reference was able to response to patrons quickly for reference questions with interactive method.

• International Journal of Knowledge Content Development & Technology
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• v.8 no.3
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• pp.53-67
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• 2018

Local languages based information storage and retrieval system is essential for any online digital repository system. This paper reports the development of an interface in Bengali that allows users not only browsing and searching Indic-script based documents but also allows administrator performing various system level operations. This paper briefly describes the origin and key characteristics of Indic-scripts along with their encoding in Unicode standard with special reference to Bengali language. It also demonstrates the development processes of Bengal-script based information representation and retrieval (IRR) system viz. BURA (Burdwan University Research Archive) using different open standard and open source software (OSS) including different factors essential for building such successful Indic-script based multilingual digital libraries. The suggested strategies may help digital library developers to design an appropriate multi-script based information access services in any other Indic-script based languages.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.155-159
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• 2017

The analog-to-digital converter (ADC) is an important component in various fields of sensor signal processing. This paper presents an expandable flash analog-to-digital converter (E-flash ADC) for sensor signal processing using a comparator, a subtractor, and a multiplexer (MUX). The E-flash ADC was simulated and designed in $0.35-{\mu}m$ standard complementary metal-oxide semiconductor (CMOS) technology. For operating the E-flash ADC, input voltage is supplied to the inputs of the comparator and subtractor. When the input voltage is lower than the reference voltage, it is outputted through the MUX in its original form. When it is higher than the reference voltage, the reference voltage is subtracted from the input value and the resulting voltage is outputted through the MUX. Operation of the MUX is determined by the output of the comparator. Further, the output of the comparator is a digital code. The E-flash ADC can be expanded easily.

• Journal of the Korean Society for information Management
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• v.24 no.4
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• pp.239-254
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• 2007

In order to solve the problems of the digital library's Interoperability and integrated management, we analyzed core technologies for interoperability in digital library in terms of information creation, organization, service. And then we proposed information technology reference model that is composed of 7 scopes. The proposed scope included 1)Metadata Management, 2)Library Services, 3)Service Integration 4)Service Management, 5)Open Interface, 6)Network, 7)Architecture. Those results can be used as a framework for developing interoperable digital library system.

• Journal of Korean Library and Information Science Society
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• v.35 no.4
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• pp.215-228
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• 2004

Discussion on the use of the library service should be based on both theoretical research and practical experiences. To increase the usage level of digital reference services in Korea, various aspects of the promotion, including latent user profile, publicity, site accessibility, and evaluation are examined, based on the previous research and overseas successful approaches. Results revealed useful information for planning and implementation.