• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.922-924
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• 1996

This paper presents the construction of Digital DAS system for supervising of power system simulator (KERISIM) which is developed in KERI. This system is composed of input transducer, input conditioner and digital supervisor. In order to watch P,Q,V,I, Power Factor and RMS in KERISIM successively, Digital arithmetic algorithm is accomplished to calculate Real/Reactive power from voltage/current data which is transferred by secondary part of CT/PT in simulator.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.206-211
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• 1998

In audio techniques calculation of digital filters is accelerated considerably by use of wave variables instead of voltages and currents. The suitability of wave variables for digital simulation of power converters was investigated and the results are reported in this paper. The original method is described briefly, modelling of switches and diode rectifiers is presented, examples are given and the features of the method are discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.97-101
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• 2013

There is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication consists of a master unit (MU) and a slave unit (SU). The MU transmits data to SU using digital optical signals. However, digital optical units that are commercially available or are under development transmit data using two's complement representation. At low input levels, a large number of SSOs (simultaneous switching outputs) are required because of the high rate of bit switching in two's complement, which thereby increases the power noise. This problem reduces the overall system capability because a DSP (digital signal processor) chip (FPGA, CPLD, etc.) cannot be used efficiently and power noise increases. This paper proposes a change from two's complement to a more efficient method that produces less SSO noise and can be applied to existing digital optical units.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.1-7
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• 2010

This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.891-897
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• 2013

The power system frequency plays an important role in monitoring and controlling the power system. The frequency can be measured through discrete Fourier transform (DFT) coefficients of its positive fundamental frequency. The accuracy of the frequency estimate is severely affected by noise in the power system signal and the leakage effect of the negative fundamental frequency in DFT. This paper proposes a DFT-based frequency estimation algorithm to cope with the noise as well as the leakage effect. In this algorithm, two suitable digital filters are introduced to reduce efficiently frequency estimate error due to the noise. These filters are designed to use a digital bandpass filter and a second-degree integrator. The effectiveness of the proposed algorithm in reduction of frequency estimate error is verified through simulations on noise, harmonics and frequency deviation.

• Journal of Power Electronics
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• v.4 no.3
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• pp.152-160
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• 2004

This paper presents analysis, modeling, and design of a low-harmonic, isolated, active-clamped SEPIC for future avionics applications. Simpler converter dynamics, high switching frequency, zero voltage-Transition-PWM switching, and a single-layer transformer construction result. This paper describes complete design of a digital controller for a high-frequency switching power supply. Guidelines for the minimum required resolution of the analog-to-digital converter, the pulse-width modulator, and the fixed-point computational unit is derived. A design example based on a SEPIC converter operating at the high switching frequency is presented. The controller design is based on direct digital design approach and standard root-locus techniques.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.178-178
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• 2000

In this paper, intelligent methods using digital protection relay in power management and control system is developed in order to protect power systems by means of timely fault detection during operation and control at starting for induction motor which have various load environments and capacities in power systems. The digital protective relay was designed with DSP CPU(TMS320C31) to Protect and measure more quickly and precisely. The test result on the basis of KEMCl120 and IEC60255, show that the operation time error of the digital motor protection relay is improved within $\pm$5%. Also, we can control motors at starting according to starting types with simple method as programmable sequence editor. So we can improve the demerits of high cost and much manhour for rework.

• Journal of the Korean Society of Industry Convergence
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• v.4 no.3
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• pp.263-266
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• 2001

In this paper, intelligent methods using digital protection relay in power SCADA system is developed in order to protect power systems by means of timely fault detection during operation and control at starting for induction motor which have various load environments and capacities in power systems. The digital protective relay was designed with DSP CPU(TMS320C31) to protect and measure more quickly and precisely. The test result on the basis of KEMC 1120 and IEC60255, show that the operation time error of the digital motor protection relay is improved within ${\pm}5%$. Also, we can control motors at starting according to starting types with simple method as programmable sequence editor. So we can improve the demerits of high cost and much manhour for rework.