• 한국ITS학회:학술대회논문집
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• 2004.11a
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• pp.236-240
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• 2004

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.607-610
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• 2006

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with hish speed frequency hopping rate and high frequency resolution characteristics was implemented in this paper. The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which ate also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provide the spurious suppression characteristic of -50 dBc, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represent the amplitude flatness of 3 dB and less in the pass-band and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.223-228
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• 2007

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with high speed frequency hopping rate and high frequency resolution characteristics was designed and implemented in this paper The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which are also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provides the spurious suppression characteristic of -50 dBc and less, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represents the amplitude flatness of 3 dB and less in the pass-band, and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.677-684
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• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.3
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• pp.217-223
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• 2013

A digital retrodirective antenna system is easy to modify and upgrade because it can control the phase information of the output signal toward opposite direction to input signal without a priori knowledge of the arrival direction. Due to this advantage, it is possible to perform fast beam tracking. In this paper, a design digital retrosirective array antenna system according to the number of antenna array by using only one digital PLL which finds angle of delayed phase and we test BER performance of this system. When we transmit data at actual communication system, the data modulated onto carrier frequency in order to shift spectrum from base band to another band. So we simulate system considering carrier frequency according to the number of antenna array. As a result, carrier frequency has no impact on the performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.209-216
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• 2013

In this paper, we design and analyze digital retrodirective array antenna (RDA) system in 60GHz wireless communication for low power consumption and high quality. Digital RDA can automatically make beam toward source without information about the direction of incoming signal, this system is able to do low power communication thanks to increased signal to interference noise ratio (SINR) because making the beam toward source can reduce interference signals. The frequency offset seriously arises when millimetric wave band like 60GHz is used to communicate for high-speed transmission. The proposed system is robustly designed to frequency offset through designing digital phase lock loop in order to solve the problem of frequency offset. In this paper, we analyze the performance of the proposed system according to the number of array antenna and frequency offset. striking space.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.