• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 춘계학술대회
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• pp.288-291
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• 2007

Since the residential load is an AC load and the output of solar cell is a DC power, the photovoltaic system needs the DC/AC converter to utilize solar cell. In case of driving to interact with utility line, in order to operate at unity power factor, converter must provide the sinusoidal wave current and voltage with same phase of utility line. Since output of solar cell is greatly fluctuated by insolation, it is necessary that the operation of solar cell output in the range of the vicinity of maximum power point. In this paper, DC/AC converter is three phase PWM converter with smoothing reactor. And then, feedforward control used to obtain a superior characteristic for current control and digital PLL circuit used to detect the phase of utility line.

• Journal of Power Electronics
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• 제10권3호
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• pp.270-276
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• 2010

In this paper, a capacitance estimation scheme for DC-link capacitors for single-phase AC/DC PWM converters is proposed. Under the no-load condition, a controlled AC current (30[Hz]) is injected into the input side, which then causes AC voltage ripples at the DC output side. Or, a controlled AC voltage can be directly injected into the DC output side. By extracting the AC voltage/current and power components on the DC output side using digital filters, the capacitance value can be calculated, where the recursive least squares (RLS) algorithm is used. The proposed methods can be simply implemented with software only and additional hardware is not required. From the experiment results, a high accuracy estimation of capacitances less than 0.85% has been obtained.

• ETRI Journal
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• 제31권4호
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• pp.357-364
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• 2009

In this paper, we propose a novel equalization on-channel repeater (OCR) with a feedback interference canceller (FIC) to relay terrestrial digital multimedia broadcasting signals in single frequency networks. The proposed OCR not only has high output power by cancelling the feedback signals caused by insufficient antenna isolation through the FIC, but also shows better output signal quality than the conventional OCR by removing multipath signals existing between the main transmitter and the OCR through an equalizer. In addition, computer simulations and laboratory test results demonstrate that the proposed OCR successfully cancels feedback signals and compensates channel distortions and provides a higher quality transmitting signal with higher output power than conventional OCRs.

• 디지털산업정보학회논문지
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• 제5권4호
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• pp.1-9
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• 2009

It establishes the nonlinear optics material recently on solid-state laser output side and from the infrared ray until is early has in the ultraviolet rays and the wavelength of broadband there makes be a possibility of getting the laser light which and in processing and measuring field it is widely used. Consequently, it used the pulse reiteration law from origination and nine as the fundamental wave direct plan it produced. intense it affixed the nonlinear optics material (KTP) in pulsed light and it got the green light. When inflicting a same energy in respectively reiteration mesh, intense interrelation of pulse light output and green light output between. It analyzed the conversion ratio which it follows in the mesh.

• ETRI Journal
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• 제29권1호
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• pp.70-78
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• 2007

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow low-voltage circuit operation. A simple 1-bit first-order delta-sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 ${\mu}m$ CMOS technology and draws less than 200 ${\mu}A$ from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non-linearity error.

• 조명전기설비학회논문지
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• 제27권10호
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• pp.59-68
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• 2013

This paper proposes the boost type bidirectional DC/DC converter with high efficiency for electric vehicle using an interleave method. This interleave method can reduce the system size because it reduces the ripple of output voltage and input current with no add to extra filter. Proposed system is consist of two converters and applies to interleaved method through phase shift to each converter. And it implements the high boost through voltage double and series construction of output port. Also, it reduces the price and increases the efficiency as operating the ZCS by leakage inductance of transformer and capacitor of voltage double with not add special reactor. Proposed DC/DC converter using interleave method is proved the validity through the result of PSIM simulation and experiment of 5kW DC/DC converter.

• 전기의세계
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• 제22권1호
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• pp.35-41
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• 1973

An automatic point traffic control method is recommended for more idealistic traffic flow over coarse road netowrks. The automatic control apparatus recommended, consists of a transceiver, amplifier, digital-to-analog converter, signal light controller for emergency and steady state, and digital counter as monitor. The transmitter sends a signal to the target vy means of Microwave-FM-CW and a diode detector picks up the echo signal. Thus the operation of the entire system will be carried out through an open loop state. Some factors necessary for an ideal detector system are rapid response, longevity and stability. An analytical method of the Doppler effect substitutes the conventional frequency deviation into the amplitude of detector output. The changing rate of amplitude is proportional to the voltage of the detector output. Some induced formula from Maxwell's radiation field theory ensures this new method, and, new method, and proves the fact with an experimental data presentation. Stability depends upon Klystron as an oscillator and a diode as a detector. the transceiver installation affects on the response and sensitivity of the system. In accordance with the detector output, several targets are easily classified by amplitudes on the scope. The traffic flow, i.e., target movement which is analyzed by the amplitude method, is shown through the scope and indicates it on the digital counter. The best efficiency for the amplitude analysis can be attained through use of an antenna having the highest sensitivity.

• 대한전자공학회논문지TC
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• 제44권3호
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• pp.92-97
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• 2007

스위칭 모우드 증폭기를 마이크로파 대역에서 이용하고자 하는 많은 연구가 있으며, 이러한 증폭기 중 E급 증폭기는 이론적으로 스위칭 동작을 통해 100%의 효율을 얻을 수 있다. 본 논문에서는 2.4GHz 대역 마이크로파 E급 증폭기로 출력 전력이 17.6dBm, 66%의 전력부가효율을 갖는 설계된 증폭기를 무선 랜 송신부에서 사용하기 위해 증폭기의 비선형 왜곡을 보상하고자 테이블 참조기법(Look Up Table)을 이용한 기저대역 사전왜곡 기법을 적용하였다. 설계된 증폭기는 -3dBm의 입력 무선랜신호를 인가하였을 때 출력스펙트럼 측정 결과가 IEEE 무선랜 스펙트럼 마스크 표준규격을 만족하며, 기저대역 사전왜곡을 적용하였을 때 중심주파수에서 20MHz offset인 주파수에서 최대 5dB의 ACPR 특성이 향상되었다.

• 한국통신학회논문지
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• 제31권7A호
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• pp.725-733
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• 2006

본 논문에서는 ATSC 지상파 디지털TV 방송신호를 중계하는 EDOCR 시스템에서 송수신신호의 주파수 동기를 위해 제안된 알고리즘에 대해 기술한다. 또한 수학적 등가모델을 사용하여 제안 알고리즘을 검증하고 제안 알고리즘을 적용한 EDOCR시스템의 성능을 분석하였다. 제안하는 알고리즘은 주 송신신호의 동기복원 과정에서 획득한 주파수 오차정보를 재 변조 과정에 사용함으로써 GPS와 같은 별도의 부가 장치 없이 송수신신호의 주파수를 일치시킬 수 있고, ATSC 송신신호 규격을 만족시키는 재전송신호를 발생시킬 수 있다.

• 융합신호처리학회논문지
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• 제12권2호
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.