• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.712-720
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• 1994

In digital mobile communication systems, the convolutional coding is considered as the optimum error correcting scheme. Recently, the Viterbi algorithm is widely used for the decoding of convolutional code. Most Viterbi decoder has been proposed in conde rate R=1/2 or 2/3 with memory components (m) less than 3. which degrades the error correcting capability because of small code constraints (K). We consider the design method for typical code rate R=1/2, K=7(171,133) convolutional code with memory components, m=6. In this paper, a novel construction method is presented which combines maximum likelihood decoding with a state transition double detection and comparison method. And the designed circuit has the error-correcting capability of random 2 bit error. As the results of logic simulation, it is shown that the proposed Viterbi decoder exactly corrects 1 bit and 2 bit error signal.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• Journal of Intelligence and Information Systems
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• v.11 no.2
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• pp.47-57
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• 2005

In this research, the main theme is the system integration of driving simulator and unmanned vehicle. The total system is composed of the mater system and the slave system. The master system has a cockpit system and the driving simulator. The slave system means an unmanned vehicle, which is composed of the actuator system the sensory system and the vision system. The communication system is composed of RS-232C serial communication system which combines the master system with the slave system. To integrate both systems, the signal classification and system characteristics considered DSP(Digital Signal Processing) filter is designed with signal sampling and measurement theory. In addition, to simulate the motion of tele-operated unmanned vehicle on the driving simulator, the classical washout algorithm is applied to this filter, because the unmanned vehicle does not have a limited working space, while the driving simulator has a narrow working space and it is difficult to cover all the motion of the unmanned vehicle. Because the classical washout algorithm has a defect of fixed high pass later, fuzzy logic is applied to reimburse it through an adaptive filter and scale factor for realistic motion generation on the driving simulator.

• Korean Journal of Remote Sensing
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• v.10 no.2
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• pp.37-48
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• 1994

In spatial information processing, particularly in non-renewable resource exploration, the spatial data sets, including remote sensing, geophysical and geochemical data, have to be geocoded onto a reference map and integrated for the final analysis and interpretation. Application of a computer based GIS(Geographical Information System of Geological Information System) at some point of the spatial data integration/fusion processing is now a logical and essential step. It should, however, be pointed out that the basic concepts of the GIS based spatial data fusion were developed with insufficient mathematical understanding of spatial characteristics or quantitative modeling framwork of the data. Furthermore many remote sensing and geological data sets, available for many exploration projects, are spatially incomplete in coverage and interduce spatially uneven information distribution. In addition, spectral information of many spatial data sets is often imprecise due to digital rescaling. Direct applications of GIS systems to spatial data fusion can therefore result in seriously erroneous final results. To resolve this problem, some of the important mathematical information representation techniques are briefly reviewed and discussed in this paper with condideration of spatial and spectral characteristics of the common remote sensing and exploration data. They include the basic probabilistic approach, the evidential belief function approach (Dempster-Shafer method) and the fuzzy logic approach. Even though the basic concepts of these three approaches are different, proper application of the techniques and careful interpretation of the final results are expected to yield acceptable conclusions in cach case. Actual tests with real data (Moon, 1990a; An etal., 1991, 1992, 1993) have shown that implementation and application of the methods discussed in this paper consistently provide more accurate final results than most direct applications of GIS techniques.

• Cross-Cultural Studies
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• v.51
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• pp.103-131
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• 2018

This study examines motivations for international students to study abroad at Korean universities. Employing qualitative and mixed methods, this study used grounded theory to analyse data obtained from student interviews, essays, digital storytelling videos, and student video representations to explicate the nature of study of six subjects. All subjects were enrolled in English Education courses during years 2014-2017. The researcher was the course instructor. Results from this study revealed that major codes that emerged from data analyses were those of economics, culture, language study, and personal development, corroborating with findings of most research literature regarding international students' motivations (OUSO, 2015). However, survey of professional literature and study data showed that motivational codes presented in the literature and this study, were discursive in nature in that each code was not only connected to all other codes, but also mutually co-constructive. As such, this study suggests that motivational codes found in study abroad literature were discursive in nature, resembling Bourdieu's (1991) theory of economic, social, and cultural capitals. Results of this study suggest that various motivations for studying abroad are subsumed under economic logic of expense and career development.

• Advances in nano research
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• v.7 no.3
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• pp.209-221
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• 2019

Graphene, with impressive electronic properties, have high potential in the microelectronic field. However, graphene itself is a zero bandgap material which is not suitable for digital logic gates and its application. Thus, much focus is on graphene nanoribbons (GNRs) that are narrow strips of graphene. During GNRs fabrication process, the occurrence of defects that ultimately change electronic properties of graphene is difficult to avoid. The modelling of GNRs with defects is crucial to study the non-idealities effects. In this work, nearest-neighbor tight-binding (TB) model for GNRs is presented with three main simplifying assumptions. They are utilization of basis function, Hamiltonian operator discretization and plane wave approximation. Two major edges of GNRs, armchair-edged GNRs (AGNRs) and zigzag-edged GNRs (ZGNRs) are explored. With single vacancy (SV) defects, the components within the Hamiltonian operator are transformed due to the disappearance of tight-binding energies around the missing carbon atoms in GNRs. The size of the lattices namely width and length are varied and studied. Non-equilibrium Green's function (NEGF) formalism is employed to obtain the electronics structure namely band structure and density of states (DOS) and all simulation is implemented in MATLAB. The band structure and DOS plot are then compared between pristine and defected GNRs under varying length and width of GNRs. It is revealed that there are clear distinctions between band structure, numerical DOS and Green's function DOS of pristine and defective GNRs.