• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.4
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• pp.745-756
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• 2020

An ICS(industrial control system) is a complex system that safely and efficiently monitors and controls industrial processes such as electric power, water treatment, transportation, automation plants and chemical plants. Because successful cyber attacks targeting ICS can lead to casualties or serious economic losses, it becomes a prime target of hacker groups sponsored by national state. Cyber campaigns such as Stuxnet, Industroyer and TRITON are real examples of successful ICS attacks, and were developed based on the deep knowledge of the target ICS. Therefore, for incident investigation of ICSs, inspectors also need knowledge of control processes and accident investigation techniques specialized for ICSs. Because there is no applicable technology, it is especially necessary to develop techniques and tools for embedded controllers located at cyber and physical boundaries. As the first step in this research, we reviewed logging capability of 4 PLC(Programmable Logic Controller)s widely used in an ICS area, and checked whether selected PLCs generate logs that can be used for digital investigation in the proposed cyber attack scenario.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.54-65
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• 1999

As the integration ratio and operating speed increase, it has become an important problem to estimate the dissipated power during the design procedure to reduce th TTM(time to market). This paper proposed a prediction model for the maximum dissipated power of a CMOS logic gate. This model uses a calculating method. It was constructed by including the characteristics of MOSFETs, the operational characteristics of the gate, and the characteristics of the input signals. As the construction procedure, a maximum power estimation model for CMOS inverter was formed first, And then, a conversion model to convert a multiple input CMOS gate into a corresponding CMOS inverter was proposed. Finally, the power model for inverter was applied to the converted result so that the model could be applied to a general CMOS gate. We designed several CMOS gates in layout level with $0.6{\mu}m$ design rule to apply both to HSPICE simulation and to the proposed models. The comparison between the two results showed that the gate conversion model and the power estimation model had within 5% and 10% of the relative errors, respectively. Those values show that the proposed models have sufficient accuracies. Also in calculation time, the proposed models were more than 30 times faster than HSPICE simulation. Consequently, it can be said that the proposed model could be used efficiently to estimate the maximum dissipated power of a CMOS logic gate during the design procedure.

• Proceedings of the Korea Contents Association Conference
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• 2008.05a
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• pp.208-212
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• 2008

The mediacy is now evolving with the development of mankind civilization. In the evolution, mediacy shows duplicate logic of remediacy with the opposite mediacy property between immediacy and hypermediacy. The duplicate logic of remediacy is defined as a result of hypermediacy which clearly requires transparency and absorption of immediacy. Because of changes from analog to digital age and the development of image technique, At present, the era is coming when the splendid and spectacle visual speaks for the screen not well-organized script and direction. With this developing period, the research for visual effect is actively performed and advanced to the new study. Though the study of visual effects contains the hypermediacy trait, it is also conjugated as a research field for immediacy on the screen which is the wish of content production directors. In this study, the analysis of case study for the movie "The Lord of The ring"'s visual effect application is carried out. Also, it is investigated that visual effects can guarantee for the verification of valuable new research filed which insure transparency and absorption in the hypermediacy results. Furthermore, on this study, it is executed for the contribution of the identity and systematization in the new research field "Visual Effects".

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.464-466
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• 2019

Controllers used in nuclear power plants require high reliability. A controller including a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (referred to hereinafter as FPGA) has been applied to many Nuclear Power Plants (NPP) in the past, including the APR1400 (Advanced Power Reactor 1400), a Korean digital nuclear power plant. Initially, the FPGA was considered as a general IC (Integrated Circuit) and verified only by device verification and performance testing. In the 1990s, research on FPGA verification began, and until the FPGA became a chip, it was regarded as software and the software Verification and Validation (V&V) using IEEE 1012-2004 was implemented. Currently, IEC 62566, which is a European standard, has been applied for a lot of verification. This method has been evaluated as the most sensible method to date. This is because the method of verifying the characteristics of SoC (System on Chip), which has been a problem in the existing verification method, is sufficiently applied. However, IEC 62566 is a European standard that has not yet been adopted in the United States and maintains the application of IEEE 1012 for FPGA. IEEE 1012-2004 or IEC 62566 is a technical standard. In practice, various methods are applied to meet technical standards. In this paper, we describe the procedure and important points of verification method of Nuclear Safety Class FPGA applying SoC verification method.

• Knowledge Management Research
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• v.23 no.2
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• pp.15-35
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• 2022

With the development of virtual and augmented reality technologies, the metaverse, a digital world that provides an immersive feeling like the real world, is overgrowing. Many IT companies such as Naver, Facebook (Meta), and NVIDIA are developing innovative technologies and launching the Metaverse platform and related products on the market. However, even though it is a new business in which many global big tech companies are aggressively investing, the results are not yet precise compared to the market expectations, and the rate of increase in the number of users is gradually slowing down. This can be attributed to the lack of consideration and understanding about how to grow the metaverse ecosystem and operate & harmonize various users/components from the time the metaverse platform was designed. In order to propose a better solution to these problems, this study adopts the yin-yang and five elements theory, which was created to understand the operation logic and logic of the human world for thousands of years. This research would like to propose a theory of double lines-five elements by defining two essential spaces of the metaverse platform, online and offline, and five essential elements constituting the metaverse platform. This study intends to provide a theoretical lens on how to design and operate a platform through the double lines and five elements theory and the concept of coexistence and polarity between the five elements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.17-22
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• 2006

CMOS LC VCO with fast response adaptive frequency calibration (AFC) technique for IEEE 802.11a/b/g WLANs is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing tecknique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched- capacitor bank is used and a wide-range digital logic quadricorrelator (WDLQ) is implemented for fast frequency detector.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.58-65
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• 2015

This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.

• Transactions of the KSME C: Technology and Education
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• v.4 no.1
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• pp.63-71
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• 2016

Although mechatronics education in a mechanical engineering curriculum is recently recognized as important, its experimental education has been done generally in the laboratory equipped with all the apparatus and could not be done at home by students. This paper introduces experimental educations on mechatronics, e.g., digital logic circuits, 7-segment LED drive, square wave generation, microcontroller programming using assembly and C languages, timer interrupt, and step motor drive using a small 5 V power supply, a breadboard, various electronic and electric components, a microcontroller and its programmer, a step motor, and a student's PC. In the developed mechatronics course, experimental educations are scheduled in parallel with content's lectures together, and cheap and economic experimental environment is prepared for students in which students can easily practice experimental works in advance or later at home by themselves.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.42-50
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• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.