• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.11
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• pp.1637-1644
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• 2003

Stereoscopic particle image velocimetry is a measurement technique to acquire three dimensional velocity field by two cameras. With a laser sheet illumination, the third velocity component can be deduced from out-of$.$plane velocity components using a stereoscopic matching method. Most industrial fluid flows are three dimensional turbulent flows, so it is necessary to use the stereoscopic PIV measurement method. However the existing stereoscopic PIV system seems hard to use since it is very expensive and complex. In this study we have developed a Miniature Stereo-PIV(MSPIV) system based on the concept of the Miniature PIV system which we have already developed. In this paper, we address the design and some primitive experimental results of the Miniature Stereo-PIV system. The Miniature Stereo-PIV system features relatively modest performances, but is considerably smaller, cheaper and easy to handle. The proposed Miniature Stereo-PIV system uses two one-chip-only CMOS cameras with digital output. Only two other chips are needed, one for a buffer memory and one for an interfacing logic that controls the system. Images are transferred to a personal computer (PC) via its standard parallel port. No extra hardware is required (in particular, no frame grabber board is needed).

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.753-758
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• 2002

In this paper, low voltage 3V CMOS programmable gain amplifier(PGA) for using in the transmitter and receiver of ADSL analog front-end is designed. The designed receive PGA is connected with 1.1MHz continuous lowpass fillet and controls the gain from 0dB to 30dB. And also the transmitter PGA is connected with 138KHz lowpass filter and controls the gain from -15dB to 0dB. The gain of All PGAs can be programmed by digital logic circuits and main controller. The designed PGAs are verified using HSPICE simulation with $0.35\mu{m}$ CMOS parameter.

• Journal of Korea Multimedia Society
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• v.9 no.12
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• pp.1607-1616
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• 2006

The growing market of multimedia and digital signal processing requires significant data-path portions of SoCs. However, the common models for verification are not suitable for SoCs. A novel model--WGL (Weighted Generalized List) is proposed, which is based on the general-list decomposition of polynomials, with three different weights and manipulation rules introduced to effect node sharing and the canonicity. Timing parameters and operations on them are also considered. Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits. The model is proved to be a uniform and efficient model for both bit-level and word-level functions. Then Based on the WGL model, a backward-construction logic-verification approach is presented, which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than $O(n^{3.6})$ and space complexity is less than $O(n^{1.5})$) without hierarchical partitioning. Finally, a construction methodology of word-level polynomials is also presented in order to implement complex high-level verification, which combines order computation and coefficient solving, and adopts an efficient backward approach. The construction complexity is much less than the existing ones, e.g. the construction time for multipliers grows at the power of less than 1.6 in the size of the input word without increasing the maximal space required. The WGL model and the verification methods based on WGL show their theoretical and applicable significance in SoC design.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.116-118
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• 2005

STSAT-2 is first satellite which is scheduled to launch by first Korea launcher. After launch Ground station Baseband Controller(GBC) for operating STSAT-2 is now developing. GBC control data flow path between satellite operation computers and ground station antennas. and GBC count number of received data packets among demodulated audio signals from three antennas and set data flow path to good-receiving antenna automatically. In GBC two uplink FSK modulators(1.2kbps, 9.6kbps) and six downlink FSK demodulators(9.6kbps, 38.4kbps) are embedded. STSAT-2 GBC hardware is more simpler than STSAT-1 GBC by using FPGA in which all digital logic implemented. Now test and debugging of GBC hardware and Software(FPGA Code and GBC Manager Program) is well progressing in SaTReC, KAIST. This paper introduce GBC structure, functions and test results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.60-64
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• 2007

In this paper, we designed FFT for European DTV and implemented system with Stratix EP1S25F672C6 FPGA At the implemented FFT, we used SIC architecture. SIC architecture is composed of algorithm-specific processing element, RAM memory, registers, and a central or distributed control unit. Designed FFT was acceptable either 2K or 8K point FFT processing, and is selectable guard interval such as 1/4, 1/8, 1/16, 1/32. Consequently, it was suitable for the standard of DVB-T(Digital Terrestrial Video Transmission System) specification. It resulted in 12% of total logic gate and 53% of total memory bit in Stratix device.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.27-35
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• 2012

In this paper, we look into a Jong Nang Channel which is the origin of digital communications and has been used in Jeju Island since AD 1234. It is one kind of communication ways which informs people of whether a house owner is in one's house or not using its own protocol. It is comprised of three timber and two stone pillars whose one side has three holes respectively. In this paper, we analyze the Jong-Nang Channel both in the light of logic and bit error probability. In addition, we compare it with a conventional binary erasure channel when some errors occur over them respectively. We also show that a capacity of NOR channel approaches Shannon limit.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.166-172
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• 1998

Switched reluctance motor(SRM) has the advantages of simple structure, low rotor inertia and high efficiency. However, position sensor is essential in SRM in order to synchronize the phase excitation to the rotor Position. The Position sensors increase the cost of drive system and tend to reduce system reliability. This paper investigates the speed control of sensorless SRM in which the Phase current and change rate are utilized in position decision, and the period of dwell angle is variable for speed control. The proposed system consists of Position decision circuit, speed controller, digital logic commutator, switching angle controller and inverter The performances in the proposed system are verified through the experiment.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.10
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• pp.903-910
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• 2000

In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.85-95
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• 2000

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2003.10a
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• pp.201-206
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• 2003

In this paper, it is presented a new technique to the design and real-time implementation of fuzzy control system based-on digital signal processors in order to improve the precision and robustness for system of industrial robot. Fuzzy control has emerged as one of the most active and fruitful areas for research in the applications of fuzzy set theory, especially in the real of industrial processes. In this thesis, a self-organizing fuzzy controller for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, In the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult, SOFC is proposed fir a hierarchical control structure consisting of basic level and high level that modify control rules. The proposed SOFC scheme is simple in structure, fast in computation and suitable for implementation of real-time control. Performance of the SOFC is illustrated by simulation and experimental results for robot with eight joints.