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2K/8K FFT Implementation with Stratix EP1S25F672C6 FPGA for DVB  

Min, Jong-Kyun (Tamul Multimedia)
Cho, Joong-Hwee (University of Incheon)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.8, 2007 , pp. 60-64 More about this Journal
Abstract
In this paper, we designed FFT for European DTV and implemented system with Stratix EP1S25F672C6 FPGA At the implemented FFT, we used SIC architecture. SIC architecture is composed of algorithm-specific processing element, RAM memory, registers, and a central or distributed control unit. Designed FFT was acceptable either 2K or 8K point FFT processing, and is selectable guard interval such as 1/4, 1/8, 1/16, 1/32. Consequently, it was suitable for the standard of DVB-T(Digital Terrestrial Video Transmission System) specification. It resulted in 12% of total logic gate and 53% of total memory bit in Stratix device.
Keywords
DVB-T; OFDM; SIC; FPGA;
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