• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.75-80
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• 1992

This paper deals with the design scheme of the custom control circuit for optimizing the interface of peripheral devices to general-purpose controllers for the high speed digital system. When the various peripheral devices such as memory, I/O devices and buffers which operate at low speed are interfaced to the microprocessor which operates at high speed, inserting the proper wait state to the processor is required. The proposed scheme designed with random logic may be applied to the high performance graphic system like the X-terminal. This circuit provides the flexibility and system independancy for the optimum digital system design.

• 제어로봇시스템학회:학술대회논문집
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• 1999.10a
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• pp.61-64
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• 1999

In this paper, a technique to expand the Input and Output (I/O) of the programmable logic controller (PLC) using remote I/O module is presented. The controller and the remote I/O module should have the same protocol and are interfaced through RS 485. Each remote I/O module consists of 16 digital input and 16 digital output, and the maximum of 32 remote I/O module can be linked to one controller. The remote I/O is programmed for interrupt request to controller independently. Therefore, there is no affect to the scan time of the controller. Using this technique, the PLC can be efficiently applied to the several hundred meters different control points such as the ON-OFF control fur the agriculture farm, the building automation system, a multi group of machine control.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.183-186
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• 2000

In this paper we propose a new architecture of a programmable digital automatic gain controller(AGC) for analog interface in mixed mode systems. Compared with conventional analog AGCs which have difficulties in integration due to large capacitors, the proposed AGC is easily integrated. So the production cost can be reduced. In addition, The proposed AGC has a better performance in temperature, and power supply variations, and substrate noise than analog counterparts do. To prevent erroneous operations of the AGC due to noise, a mal-function preventer is newly proposed. In addition, to achieve an optimized AGC time constant, we propose a logic block which controls an up-down counting clock. This is directly related to the changing speed of the AGC gain. Implemented with a 0.25 $\mu\textrm{m}$ 1-poly, 5-metal CMOS parameters, the AGC operates from a single 2.5V power supply with the dynamic range of 36.ldB and occupies active area of 500$\mu\textrm{m}$${\times}$600$\mu\textrm{m}$

• Nuclear Engineering and Technology
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• v.29 no.6
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• pp.433-443
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• 1997

In this work, an analytic approach to the dependability of software in the operational phase is suggested with special attention to the hardware fault effects on the software behavior : The hardware faults considered are memory faults and the dependability measure in question is the reliability. The model is based on the simple reliability theory and the graph theory which represents the software with graph composed of nodes and arcs. Through proper transformation, the graph can be reduced to a simple two-node graph and the software reliability is derived from this graph. Using this model, we predict the reliability of an application software in the digital system (ILS) in the nuclear power plant and show the sensitivity of the software reliability to the major physical parameters which affect the software failure in the normal operation phase. We also found that the effects of the hardware faults on the software failure should be considered for predicting the software dependability accurately in operation phase, especially for the software which is executed frequently. This modeling method is particularly attractive for the medium size programs such as the microprocessor-based nuclear safety logic program.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.3
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• pp.75-83
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• 2011

Cognitive radio (CR) technology is to maximize the spectrum utilization by allocating the unused spectrums to the unlicensed users. This technology enables the sharing of channels among secondary (unlicensed) and primary (licensed) users on a non-interference basis after sensing the vacant channel and as a result, it is possible to harness wireless frequency more efficiently. To enhance the accuracy of sensing, RDSS was suggested. It is a fusion mechanism based on the reputation of sensing nodes and WSPRT (weighted sequential probability ratio test). However, in RDSS, the execution number of WSPRT could increase according to the order of inputted sensing values, and the fast defense against the forged values is difficult. In this paper, we propose a transaction signing-based authentication scheme for secure distributed spectrum sensing to response the forged values. The validity of proposed scheme is provided by BAN logic.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.3
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• pp.55-61
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• 2011

This paper presents an implementation of Lattice Reduction (LR)-aided detector for Multiple-Input Multiple-Output (MIMO) system using Graphics Processing Unit (GPU). GPU is a parallel processor which has a number of Arithmetic Logic Units (ALUs), thus, it can minimize the operation time of LR algorithm through the parallelization using multiple threads in the GPU. Through the implemented LR-aided detector, we verify that the LR-aided detector operates a lot faster than Maximum Likelihood (ML) detector. The implemented LR-aided detector has been applied to WiMAX system to show the feasibility of its real-time processing. In addition, we demonstrate that the processing time can be reduced at the cost of 3dB SNR loss by limiting the repeating loop in Lenstra-Lenstra-Lovasz (LLL) algorithm which is frequently used in LR-aided detector.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2490-2492
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• 2001

According to the appearance of various virtual websites using multimedia technologies for engineering education, the internet applications in engineering education have drawn much interests. But unidirectional communication, simple text/image-based webpages and tedious learning process without motivation etc. have made the lowering of educational efficiency in cyberspace. Thus, to cope with these difficulties this paper presents a web-based educational Java applets for understanding the principles or conceptions of digital logic systems. The proposed Java applets provides the improved learning methods which can enhance the interests of learners. The results of this paper can be widely used to improve the efficiency of cyberlectures in the cyber university. Several sample Java applets are illustrated to show the validity of the proposed learning method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.3
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• pp.87-95
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• 2012

Up to now, industrial cranes play important roles as the effective machines to carry heavy loads in the manufacturing premise, in the construction field and so on. And, a crane is widely used not only to daily work but also to carry heavy materials efficiently in a construction site for prevention of accident. However, the crane operation is highly complicated even for experts. In this paper, we developed the content of the crane mounted on the controller. This content overload conditions in the operating environment for the crane operator to warn, and the operation of equipment has the capability to limit automatically. The content for crane controller is to alert the operator overload and to limit the operation of equipment for stabilizing capabilities. The content of the flexible algorithm is based on stabilizing controllers, PLC (Programmable Logic Controller) to connect for using the equipment and electrical control systems to ensure the safety of workers and to improve the ability to work possible.