• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• 한국IT서비스학회지
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• 제12권2호
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• pp.1-12
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• 2013

A new form of software piracy known as digital piracy has taken the spotlight. Lost revenues due to digital piracy could reach 2,500 billion won in year 2010 alone. This paper examines the causal relationships among the attitude toward digital piracy, subjective norm, economic gain, political efficacy, school policy, etc, in a university setting. Results from survey responses indicate that the social norm and economic gain affect the attitude toward digital piracy, and that school policy influences the subjective norm as well as political efficacy. But, contrary to our expectation, political efficacy has been found to have no impact on the social norm and economic gain. Prior learning experiences have been shown to affect economic gain, but not the subjective norm. As a conclusion, the academic and practical implications of these findings are discussed.

• 전자공학회논문지
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• 제51권2호
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• pp.46-52
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• 2014

본 논문은 다중 이득 제어를 통하여 빠른 lock-time을 갖는 디지털 위상 주파수 검출기 회로를 제안한다. 기준신호와 피드백 신호의 위상 차이가 클 때, 위상 차이가 적으면서 lock에 근접했을 때, lock 이후의 세 경우에 따라 디지털 위상 동기 루프의 이득을 다르게 설정하여 lock-time을 효과적으로 줄일 수 있다. 시뮬레이션 결과를 통해 제안된 기법을 적용함으로써 기존의 단일 이득 제어 구조보다 lock-time을 약 100배 개선시킬 수 있음을 확인하였다.

• 융합신호처리학회논문지
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• 제2권4호
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• pp.71-76
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• 2001

본 논문에서는 5GHz 대역을 사용하는 고속 무선 LAN의 표준안의 IEEE 802.11a-1999 를 위한 디지털 자동 이득 제어기를 제언한다. 송수신간의 동기화를 위한 신호인 training symbol을 이용하여 수신기에 입력되는 신호의 이득을 측정한다. 측정된 이득을 이상적인 이득과 비교하여 갱신할 이득을 구한다. 갱신 이득은 신호를 증폭하는 GCA(Gain Controlled Amplifer)의 입력 전압으로 변환되어 신호의 증폭도를 제어하게 된다. 본 논문에서는 하드웨어 부담을 줄이기 위해 부분 선형 근사방법을 이용하여 갱신 이득을 본 논문에서 제안한 디지털 자동 이득 제어기는 VHDL을 이용하여 설계하였으며, Xilinx cAD tool을 이용하여 timing verification을 수행하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.341-344
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• 2002

This paper is proposed a 8-bit analog to digital converter for CMOS image sensor. A analog to digital converter for CMOS image sensor is required function to control gain. Frequency divider is used In control gain in this proposed analog to digital converter. At 3.3 Volt power supply, total static power dissipation is 8㎽ and programmable gain control range is 30㏈. Newly suggested analog to digital converter is designed by 0.35um 2-poly 4-metal CMOS technology.

• ETRI Journal
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• 제26권5호
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• pp.501-504
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• 2004

This paper presents a simple gain/phase blind compensation algorithm with an automatic gain control (AGC) function for the adoption of the AGC function and compensation for gain/phase imbalances in quadrature phase shift keying (QPSK) direct conversion receivers (DCRs). The AGC function is interactively operated with the compensation algorithm for gain/phase imbalances. By detecting the gain sum and difference values between the I-channel and Q-channel, the combined AGC and gain imbalance compensation algorithm provides a simpler DCR architecture.

• 대한의용생체공학회:의공학회지
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• 제28권2호
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• pp.199-204
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• 2007

In digital radiography, to improve the contrast of digital radiography image, the multi-scale nonlinear amplification algorithm based on unsharp masking is one of the major image enhancement algorithms. In this paper, we used the Laplacian pyramid to decompose a digital radiography(DR) image. In our simulation, the DR image was decomposed into seven layers and the coefficients of the each layer was amplified with nonlinear function. We also imported a noise containment algorithm to limit noise amplification. To enhance the contrast of image, we proposed a new adaptive non-linear gain amplification coefficients. As a result of having applied to some clinical data, a detail visibility was improved significantly without unacceptable noise boosting. Images that acquired with the proposed adaptive non-linear gain coefficients have shown superior quality to those that applied similar gain control method and expected to be accepted in the clinical applications.

• 전기전자학회논문지
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• 제25권2호
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• pp.302-308
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• 2021

본 논문에서는 영상 처리용 12-비트의 10-MS/s 파이프라인 아날로그-디지털 변환기(ADC: analog-to-digital converter)가 제안된다. 제안된 ADC는 샘플-홀드 증폭기, 3개의 stage, 3-비트 플래시 ADC, 그리고 digital error corrector로 구성된다. 각 stage는 4-비트 flash ADC와 multiplying digital-to-analog ADC로 구성된다. 고해상도의 ADC를 위해 제안된 샘플-홀드 증폭기는 gain boosting을 이용하여 전압 이득을 증가시킨다. 제안된 파이프라인 ADC는 1.8V 공급전압을 사용하는 180nm CMOS 공정에서 설계되었고 차동 1V 전압을 가지는 1MHz 사인파 아날로그 입력신호에 대해 10.52-비트의 유효 비트를 가진다. 또한, 약 5MHz의 나이퀴스트 사인파 입력에 대해 측정된 유효비트는 10.12 비트이다.