• Journal of information and communication convergence engineering
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• v.17 no.3
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• pp.221-226
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• 2019

In this work, a transmitter/receiver front-end module (T/R FEM) with an automatic Tx/Rx switching scheme for a 2.4 GHz microwave power transfer is developed for a retro-reflective beamforming scheme. Recently, research on wireless power transfer techniques has moved to wireless charging systems for mobile devices. Retro-reflective beamforming is a good candidate for tracking the spatial position of a mobile device to be charged. In Tx mode, the T/R FEM generates a minimum of 1 W. It also comprises an amplitude and phase monitoring port for transmitting RF power. In Rx mode, it passes an Rx pilot signal from a mobile device to a digital baseband subsystem to recognize the position of the mobile device. The insertion loss of the Rx signal path is 4.5 dB. The Tx and Rx modes are automatically switched by detecting the Tx input power. This T/R FEM is a design example of T/R FEMs for wireless charging systems based on a retro-reflective beamforming scheme.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.66-72
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• 2009

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.118-125
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• 2008

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1424-1428
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• 2004

In this paper, CMOS analog filters for use in the Analog front End of digital subscriber loop(DSL) chip set are proposed. Designed filters contain receiver continuous-time filters which are composed of lowpass and highpass functions. And their cutoff frequency are 138H1z and 1.1MHz respectively. A low-voltage gm-c integrator is improved and used to design filters. Desisned filters are verified by HSPICE simulation with the 0.25${\mu}m$ CMOS n-well parameter.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.391-394
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• 2006

The paper deals with the experimental GNSS receiver built at the Czech Technical University for experiments with the real GNSS signal. The receiver is based on software defined radio architecture. Receiver consists of the RF front end and a digital processor based on programmable logic. Receiver RF front end supports GPS L1, L2, L5, WAAS/EGNOS, GALILEO L1, E5A, E5B signals as well as GLONASS L1 and L2 signals. The digital processor is based on Field Programmable Gate Array (FPGA) which supports embedded processor. The receiver is used for various experiments with the GNSS signals like GPS L1/EGNOS receiver, GLONASS receiver and investigation of the EGNOS signal availability for a land mobile user. On the base of experimental GNSS receiver the GPS L1, L2, EGNOS receiver for railway application was designed. The experimental receiver is also used in GNSS monitoring station, which is independent monitoring facility providing also raw monitoring data of the GPS, EGNOS and Galileo systems via internet.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.462-468
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• 2012

In this paper, an adaptive digital automatic gain control(AGC) algorithm with two stages is proposed. AGC technique is crucial for mobile communication equipment because path loss in wireless channel and gain fluctuation in receiver front-end continuously change the received signal strength. Furthermore, adaptive criteria should be applied to the design of AGC algorithm in order to support many waveforms with one SDR communication device. With these reasons, a two-stage structure is proposed to satisfy both flexibility and adaptiveness. Compared with conventional method, it also requires shorter convergence time. Numerical results show that the gain value of variable gain amplifier(VGA) is converged within proper time and proposed scheme controls the input level of analog to digital converter(ADC) to be stable during long range of time.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.38-48
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• 2014

In this paper, a design of Signal Processing Analog Front-End IC for Automotive Piezo-Resistive Type Pressure Sensor is presented. In modern society, as the car turns to go from mechanical to electronic technology, the accuracy and reliability of electronic parts required importantly. In order to improve these points, Programmable Gain Amplifier (PGA) amplifies the received signal in accordance with gain for increasing the accuracy after PRT Sensor is operated to change physical pressure signals to electrical signals. The signal amplified from PGA is processed by Digital blocks like ADC, CMC and DAC. After going through this process, it is possible to determine the electrical signal to physical pressure signal. As processing analog signal to digital signal, reliability and accuracy in Analog Front-End IC is increased. The current consumption of IC is 5.32mA. The die area of the fabricated IC is $1.94mm{\times}1.94mm$.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.