• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.601-604
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• 2002

In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.3
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• pp.267-274
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• 2004

In this paper, a new on-line dead-time compensation method is proposed. The output voltage errors due to the dead-time effect is considered as disturbance voltages. The magnitude of the disturbance voltages is estimated using a time delay control technique and the disturbance voltages are calculated using the estimated values, measured currents, and position information. The calculated disturbance voltages are fed to voltage references in order to compensate the dead-time effect. The proposed method is applied to a PM synchronous motor drive system and implemented in a digital manner using a digital signal processor (DSP) TMS320C31. The experiments are carried out for this system to show the effectiveness of the proposed method and the results show the validity of the proposed method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.512-515
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• 2010

SIGINT(SIGnal INTelligence) includes several parameters intercepted by measurement and analysis of the RF(Radio frequency) signal from free space. One of the important parameters is frequency information. Expecially, in order to perform instantaneous frequency measurement of Radar and Missile seeker's RF signals, we use dedicated RF modules as a DFD(Digital Frequency Discriminator) to provide frequency information by measurement of the relative phase difference between signals via intended RF delay lines. It must measure and provide realtime based frequency information on short pulsed RF signal up to 100 nSec or less. This document proposes Ultra wideband DFD consisted of a RF input section of Wideband 4 channel RF delay line and correlator, a digital processing section to measure and provide frequency information from I/Q signal, and a frequency calibration section. Also, it will show design suitability based on test results measured under test condition of very short input pulse signals.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.3
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• pp.275-284
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• 2004

This paper discusses how to control the compensation voltages in dynamic voltage restorers (DVR). On analyzing the power circuit of a DVR system, control limitations and control targets are presented for the voltage compensation in DVRs. Based on the preceded power stage analysis, a novel controller for the compensation voltages of DVRs is proposed by a feed forward control scheme. This paper discusses also the time delay problems in the control system of DVRs. Digitally controlled DVR systems normally have control delay at amount of one sampling time of the control system and a half of the switching period of the DVR inverter. The control delay in digital controllers increases the dimension of the system transfer function one degree higher, which makes the control system more complicate and more unstable. This paper proposes a guide line to design the control gain, appropriate output filter parameters and inverter switching frequency for DVRs with digital controllers. Proposed theory is verified by an experimental DVR system with a full digital controller.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.8
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• pp.1-6
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• 1999

The only transmission characteristics in frequency domain is considered when using the tapered transmission line for wide-band impedance matching in MCM and MIC designs. In this paper, the distortion of an electrical pulse with rise/fall time resulting from dispersion and reflection as it propagates along a tapered microstrip line is investigated, and the delay time and distortion rate with respect to input and load impedances are analyzed on triangular and exponential tapered lines. A dispersion model of the phase constant proposed by Kirschning-Jansen is used to meet the frequency, accuracy and microstrip parametric requirements. The triangular tapered line shows both shorter delay time and higher distortion rate than those of the exponential tapered line. Furthermore, the amplitude of signal reflected from load point is calculated in time domain.

• Nuclear Engineering and Technology
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• v.52 no.10
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• pp.2339-2345
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• 2020

Radiation imaging systems consisting of a large number of channels greatly benefit from multiplexing methods to reduce the number of channels with minimizing the system complexity and development cost. In conventional pixelated radiation detector modules, such as anger logic, is used to reduce a large number of channels that transmit signals to a data acquisition system. However, these methods have limitations of electrical noise and distortion at the detector edge. To solve these problems, a multiplexing concept using a digital signal encoding technique based on a time delay method for signals from detectors was developed in this study. The digital encoding multiplexing (DEM) method was developed based on the time-over-threshold (ToT) method to provide more information including the activation time, position, and energy in one-bit line. This is the major advantage of the DEM method as compared with the traditional ToT method providing only energy information. The energy was measured and calibrated by the ToT method. The energy resolution and coincidence time resolution were observed as 16% and 2.4 ns, respectively, with DEM. The position was successfully distributed on each channel. This study demonstrated the feasibility that DEM was useful to reduce the number of detector channels.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.3
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• pp.239-248
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• 2004

Optical coherence tomography(OCT) is high resolution imaging system which can see the cross section of microscopic organs in the living tissue. In this paper, we analyze the relation between the light source and the resolution of modulated signal in Michelson interferometer. We construct 1-D OCT signal processing hardware such as amplifiers, filters, and demodulate electronic signals from the photo detector. In order to get 2-D OCT image, the synchronization among optical delay line, sample stage and A/D converter is dealt with. In experiments, we verify analog and digital signal processing blocks which apply to the stacks of glasses. Finally we aquire high resolution 2-D OCT image with respect to the onion tissue. We expect that this result can be applied to the medical instrument through performance improvement.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.420-429
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• 2004

This paper proposes a novel current control strategy on active power filters using PQR instantaneous power theory which can compensate the line current harmonics and the neutral line current under the unbalanced and/or distorted source conditions in three-phase four-wire systems. The characteristics of the inverter ac filters are analyzed and a novel digital controller are proposed to overcome the inherent time delay problem in digital controllers with designed control gain in this paper. The proposed current control method is based on a sinusoidal PWM for fully-digital implementation compared with a conventional hysteresis PWM. PSiM simulation results verify the good performance of the proposed current control strategy on shunt type APFs.