• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.6
• /
• pp.567-572
• /
• 2004

This paper shudies an automatic gain control(AGC) algorithm used in wireless communication cellular systems. The AGC design includes the selection of the appropriate analog-to-digital converter(ADC) and keeping the input power to the ADC constant to minimize the quantization noise generated from the analog-to-digital conversion process. In this paper the process to determine the required precision or the An is illustrated and the method to set the design parameters of the AGC is proposed. And the validity of the proposed algorithm is verified by computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37 no.6C
• /
• pp.462-468
• /
• 2012

In this paper, an adaptive digital automatic gain control(AGC) algorithm with two stages is proposed. AGC technique is crucial for mobile communication equipment because path loss in wireless channel and gain fluctuation in receiver front-end continuously change the received signal strength. Furthermore, adaptive criteria should be applied to the design of AGC algorithm in order to support many waveforms with one SDR communication device. With these reasons, a two-stage structure is proposed to satisfy both flexibility and adaptiveness. Compared with conventional method, it also requires shorter convergence time. Numerical results show that the gain value of variable gain amplifier(VGA) is converged within proper time and proposed scheme controls the input level of analog to digital converter(ADC) to be stable during long range of time.

• Proceedings of the IEEK Conference
• /
• 2000.06e
• /
• pp.183-186
• /
• 2000

In this paper we propose a new architecture of a programmable digital automatic gain controller(AGC) for analog interface in mixed mode systems. Compared with conventional analog AGCs which have difficulties in integration due to large capacitors, the proposed AGC is easily integrated. So the production cost can be reduced. In addition, The proposed AGC has a better performance in temperature, and power supply variations, and substrate noise than analog counterparts do. To prevent erroneous operations of the AGC due to noise, a mal-function preventer is newly proposed. In addition, to achieve an optimized AGC time constant, we propose a logic block which controls an up-down counting clock. This is directly related to the changing speed of the AGC gain. Implemented with a 0.25 $\mu\textrm{m}$ 1-poly, 5-metal CMOS parameters, the AGC operates from a single 2.5V power supply with the dynamic range of 36.ldB and occupies active area of 500$\mu\textrm{m}$${\times}$600$\mu\textrm{m}$

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.7C
• /
• pp.706-714
• /
• 2009

In this paper, we proposed a burst mode AGC loop and preamble detector applicable for VDL(VHF Digital Link) mode-2 using D8PSK modulation scheme and the performance analysis of proposed schemes is described. Generally the AGC scheme can be divided into two types, continuos and burst mode AGC. The continuos mode is performed well only with an analog feedback AGC loop. But the analog feedback AGC loop is not suitable for burst mode since its gain lock time is more than preamble duration, which causes the preamble detector misses preamble. Hence a fast digital AGC loop is required for burst mode. Also the AGC loop has to be designed with full gain during idle time to detect bursts although the signal level is very low. If the time to acquire gain lock is slow, the preamble detector fail to detect burst due to saturation of a lot of preamble samples. The receiver performance might be down even if the burst was detected because the preamble is used to estimate several parameters need to demodulation at receiver. In this paper we analysed relationships between the AGC loop and preamble detector. we present an AGC loop and preamble detector in burst mode.

• ETRI Journal
• /
• v.26 no.5
• /
• pp.501-504
• /
• 2004

This paper presents a simple gain/phase blind compensation algorithm with an automatic gain control (AGC) function for the adoption of the AGC function and compensation for gain/phase imbalances in quadrature phase shift keying (QPSK) direct conversion receivers (DCRs). The AGC function is interactively operated with the compensation algorithm for gain/phase imbalances. By detecting the gain sum and difference values between the I-channel and Q-channel, the combined AGC and gain imbalance compensation algorithm provides a simpler DCR architecture.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1990.10a
• /
• pp.115-119
• /
• 1990

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.5A
• /
• pp.341-346
• /
• 2009

M-WiMAX (Mobile-Worldwide Interoperability for Microwave Access) system, which uses OFDM (Orthogonal Frequency Division Multiplexing) technique, is known to be proper for mobile high-speed data transmission system. Nevertheless, M-WiMAX is seriously sensitive to IQ imbalance caused by the LO (Local Oscillator) at the receiver. In this paper, we analyze the effect of IQ imbalance on the system, and then propose a joint optimization scheme that can optimize DFE (Digital Front-end) of mobile modem by combining operation duplicated between AGC (Automatic Gain Control) and the estimation and compensation of IQ imbalance. Simulation results show that the proposed scheme achieves the same performance of the conventional scheme while reducing the complexity of the H/W implementation.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.48-55
• /
• 1999

This paper describes automatic gain control circuit (AGC) design techniques for CMOS CCD camera interface systems. The required gain of the AGC in the proposed system is controlled directly by digital bits without conventional extra D/A converters and the signal settling behavior is almost independent of AGC gain variation at video speeds. A capacitor-segment combination technique to obtain large capacitance values considerably improves the effective bandwidth of the AGC based on switched-capacitor techniques. A proposed layout scheme for capacitor implementation shows AGC matching accuracy better than 0.1 %. The outputs from the AGC are transferred to a 10b A/D converter integrated on the same chip. The proposed AGC is implemented as a sub-block of a CCD camera interface system using a 0.5 um n-well CMOS process. The prototype shows the 32-dB AGC dynamic range in 1/8-dB steps with 173 mW at 3 V and 25 MHz.

• Journal of Institute of Control, Robotics and Systems
• /
• v.14 no.5
• /
• pp.426-431
• /
• 2008

In this paper, an improved AE system for digital still camera is proposed. AE system is auto exposure system to maintain optimized brightness of output image. But there is limitation for mobile devices to get high quality image with the conventional AE algorithm, because of organizational restriction of system. The conventional research has been studied only electronic shutter and AGC on the AE algorithm. In this paper, we suggest new AE algorithm included target setting, frame delay, Gamma Correction as well as electronic shutter and AGC to get high quality image. The proposed algorithm show improved result at control speed and ability of luminance expression.

• ETRI Journal
• /
• v.30 no.5
• /
• pp.729-734
• /
• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.