• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• Restorative Dentistry and Endodontics
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• v.29 no.4
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• pp.386-398
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• 2004

Objectives: The purpose of this study was to observe the reaction kinetics and the degree of polymerization of composite resins when cured by different light sources and to evaluate the effectiveness of the blue Light Emitting Diode Light Curing Units (LED LCUs) compared with conventional halogen LCUs. Materials and Methods: First, thermal analysis was performed by a differential scanning calorimeter (DSC). The LED LCU (Elipar Freelight, $320{\;}mW/\textrm{cm}^2$) and the conventional halogen LCU (XL3000, $400{\;}mV/\textrm{cm}^2$) were used in this study for curing three composite resins (SureFil, Z-250 and AEliteFLO). Second. the degree of conversion was obtained in the composite resins cured according to the above curing mode with a FTIR. Third, the measurements of depth of cure were carried out in accordance with ISO 4049 standards. Statistical analysis was performed by two-way ANOVA test at 95% levels of confidence and Duncan's procedure for multiple comparisons. Results: The heat of cure was not statistically different among the LCUs (p > 0.05). The composites cured by the LED (Exp) LCUs were statistically more slowly polymerized than by the halogen LCU and the LED (Std) LCU (p < 0.05). The composite resin groups cured by the LED (Exp) LCUs had significantly greater degree of conversion value than by the halogen LCU and the LED (Std) LCU (p =0.0002). The composite resin groups cured by the LED (Std) LCUs showed significantly greater depth of cure value than by the halogen LCU and the LED (Exp) LCU (p < 0.05).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.67-76
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• 2005

This paper proposes a compact-sized surface myoelectric sensor for the myoelectric hand prosthesis. To fit the surface myoelectric sensor in the socket for the myoelectric hand prosthesis, the sensor should be a compact size. The surface myoelectric sensor is. composed of a skin interface and a single processing circuit that are mounted on a single package. The skin interface has one reference and two input electrodes, and the reference electrode is located in the center of two input electrodes. In this paper we propose two types of sensors with the circle- and bar-shaped reference electrode, but all input electrodes are the bar-shaped. The metal material of the electrodes is the stainless steel (SUS440) that endures sweat and wet conditions. Considering the conduction velocity and the median frequency of the myoelectric signal, we select the inter-electrode distance (IED) between two input electrodes as 18mm, 20mm, and 22 mm. The signal processing circuit consists of a differential amplifier with a band pass filter, a band rejection filter for rejecting 60Hz power-line noise, amplifiers, and a mean absolute value circuit. We evaluate the proposed sensor from the output characteristics according to the IED and the shape of the reference electrode. From the experimental results we show the surface myoelectric sensor with the 18mm IED and the bar-shaped reference electrode is suitable for the myoelectric hand prosthesis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.91-96
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• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.41-46
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• 2007

A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.12
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• pp.1086-1092
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• 2012

It has been studied for DGPS/INS(Differential Global Positioning System/Inertial Navigation System) to offer the more precise and reliable navigation data with the aviation industry development. The flight performance evaluation of navigation system is very significant because the reliability of navigation data directly affect the safety of aircraft. Especially, the high-level navigation system, as DGPS/INS, need more precise flight performance evaluation method. The performance analysis is performed by comparing between the DGPS/INS navigation data and reference trajectory which is more precise than DGPS/INS. The GPS receiver, which is capable of post-processed CDGPS(Carrier-phase DGPS) method, can be used as reference system. Generally, the DGPS/INS is estimated the CG(Center of Gravity) point of aircraft while the reference system is output the position of GPS antenna which is mounted on the outside of aircraft. For this reason, estimated error between DGPS/INS and reference system will include the error due to lever arm. In order to more precise performance evaluation, it is needed to compensate the lever arm. This paper presents procedure and result of flight test which includes lever arm compensation in order to verify reliability and performance of DGPS/INS more precisely.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.5
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• pp.875-888
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• 2021

In this paper, we search integral distinguishers of lightweight block cipher PIPO and propose a key recovery attack on 8-round PIPO-64/128 with the obtained 6-round distinguishers. The lightweight block cipher PIPO proposed in ICISC 2020 is designed to provide the efficient implementation of high-order masking for side-channel attack resistance. In the proposal, various attacks such as differential and linear cryptanalyses were applied to show the sufficient security strength. However, the designers leave integral attack to be conducted and only show that it is unlikely for PIPO to have integral distinguishers longer than 5-round PIPO without further analysis on Division Property. In this paper, we search integral distinguishers of PIPO using a MILP-aided Division Property search method. Our search can show that there exist 6-round integral distinguishers, which is different from what the designers insist. We also consider linear operation on input and output of distinguisher, respectively, and manage to obtain totally 136 6-round integral distinguishers. Finally, we present an 8-round PIPO-64/128 key recovery attack with time complexity 2^124.5849 and memory complexity of 2⁹³ with four 6-round integral distinguishers among the entire obtained distinguishers.

• Tunnel and Underground Space
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• v.28 no.6
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• pp.596-608
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• 2018

As urban infrastructure is aging, the possibility of accidents due to the failures or breakdowns of infrastructure increases. Especially, aging underground infrastructures like sewer pipes, waterworks, and subway have a potential to cause an urban ground sink. Urban ground sink is defined just as a local and erratic collapse occurred by underground cavity due to soil erosion or soil loss, which is separated from a sinkhole in soluble bedrock such as limestone. The conventional measurements such as differential settlement gauge, inclinometer or earth pressure gauge have a shortcoming just to provide point measurements with short coverage. Therefore, these methods are not adequate for monitoring of an erratic subsidence caused by underground cavity due to soil erosion or soil loss which occurring at unspecified time and location. Therefore, an alternative technology is required to detect a change of underground physical condition in real time. In this study, the feasibility of a novel magnetic resonance based monitoring method is investigated through laboratory tests, where the changes of path loss (S21) were measured under various testing conditions: media including air, water, and soil, resonant frequency, impedance, and distances between transmitter (TX) and receiver (RX). Theoretically, the transfer characteristic of magnetic field is known to be independent of the density of the medium. However, the results of the test showed the meaningful differences in the path loss (S21) under the different conditions of medium. And it is found that the reflection coefficient showed the more distinct differences over the testing conditions than the path loss. In particular, input reflection coefficient (S11) is more distinguishable than output reflection coefficient (S22).

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.