• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1028-1035
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• 1999

To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.1
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• pp.63-68
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• 2004

In this paper, we propose a method about the extraction of vehicle and tracking trajectory for moving vehicle tracking system in road. This system applied to the monitoring system of the traffic flow for ATMS(advanced traffic management system) of ITS(intelligent transport system). Also, this system can solve the problem of maintenance of loop sensor. And we detected vehicle using differential image analysis. Because of the road environment changes by real time. Therefore, the method to use background image is not suitable. And we used Kalman filter and innovation value and variable search area for vehicle tracking system. Previous method using fixed search area is sensitive to the moving trajectory and the speed of vehicle. Simulation results show that proposed method increases the possibility of traffic measurement more than fixed area traffic measurement system.

• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.592-600
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• 2012

Conventional methods for preparing ceramic bodies, such as cold isostatic pressing, gypsum-mold slip casting, and filter pressing are not completely suitable for fabricating large and thick ceramic plates owing to disadvantages of these processes, such as the high cost of the equipment, the formation of density gradients, and differential shrinkage during drying. These problems can be avoided by employing a pressure-vacuum hybrid slip casting approach that considers not only by the compression of the aqueous slip in the casting room (pressure slip casting) but also the vacuum sucking of the dispersion medium (water) around the mold (vacuum slip casting). We prepared the alumina formed bodies by means of pressure-vacuum hybrid slip casting with stepwise pressure loading up to 0.5 MPa using a slip consisting of 40 vol% solid, 0.6 wt% APC, 1 wt% PEG, and 1 wt% PVA. After drying the green body at $30^{\circ}C$ and 80% RH, the green density of the alumina bodies was about 56% RD. The sintered density of an alumina plate created by means of sintering at $1650^{\circ}C$ for 4 h exceeded 99.8%.This method enabled us to fabricate a $110{\times}110{\times}20$ mm alumina plate without cracks and with a homogeneous density, thus demonstrating the possibility of extending the method to the fabrication of other ceramic products.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.35 no.2
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• pp.115-121
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• 2002

To develop a new method of conjugation and to determine the distribution of R plasimds, we isolated multi-drug resistant strains from fish pathogenic bacteria in the farms of south and east seacoasts of Korea. Out of the 134 isolates examined, 10 showed resistance to chloramphenicol, tetracycline, streptomycin, ampicillin, colistin, nalidixic acid, oxolinic acid and kanamycin. One out of 10 multi-drug resistance bacteria, Vibfio damsela JE1 (V. damsela JE1), contained transferable R plasmid of chlorarnphenicol- tetracycline resistance genes and other nucleic acids encoding ampicillin and kanamycin resistance. The presence of the R plasmid was confirmed by conjugation using the chromocult medium (CC) as a selective and differential medium for transconiugants with identification based on the growth or colors of the colonies. The frequency of R plasmid transfer with filter mating method was come out much higher than that of broth mating method and appeared to be dependent upon the mating time and temperature. The optimum conditions for filter mating method were found to be 30$^{\circ}C$ and 24hrs as mating temperature and period, respectively, Moreover, donor cells with R plasmid, both isolate and standard bacteria, were shown to have an ability to transfer the plasmid against Escherichia coli K-12 HB101 (E. coli HB101) and Edwardsiella tarda (E. tarda) RE14 at fairly high frequencies, finally, we isolated 3 isolates of Sphingomonas sp., carrying R plasmid from 12 multi-drug resistant bacteria in normal microflora of the flounder (Paralichthys olivaceus) group used for the isolation of V emsela JE1 four months before. The same size and gene transfer chayateristics of R plasimds with those of V damsela JE1 confirmed that normal microflora have the reservoir activity for R plasmid in natural aquatic environment.

• Journal of Broadcast Engineering
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• v.1 no.2
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• pp.176-187
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• 1996

This paper deals with the accurate estimation of 3- D pose (position and orientation) of a moving object with reference to the world frame (or robot base frame), based on a sequence of stereo images taken by cameras mounted on the end - effector of a robot manipulator. This work is an extension of the previous work[1]. Emphasis is given to the 3-D pose estimation relative to the world (or robot base) frame under the presence of not only the measurement noise in 2 - D images[ 1] but also the camera position errors due to the random noise involved in joint angles of a robot manipulator. To this end, a new set of discrete linear Kalman filter equations is derived, based on the following: 1) the orientation error of the object frame due to measurement noise in 2 - D images is modeled with reference to the camera frame by analyzing the noise propagation through 3- D reconstruction; 2) an extended Jacobian matrix is formulated by combining the result of 1) and the orientation error of the end-effector frame due to joint angle errors through robot differential kinematics; and 3) the rotational motion of an object, which is nonlinear in nature, is linearized based on quaternions. Motion parameters are computed from the estimated quaternions based on the iterated least-squares method. Simulation results show the significant reduction of estimation errors and also demonstrate an accurate convergence of the actual motion parameters to the true values.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.83-93
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• 2013

By comparing Wiener's MMSE on stochastic signal transmission with Shannon's mutual information first proved by C.E. Shannon in terms of information theory, connections between two approaches were investigated. What Wiener wanted to see in signal transmission in noisy channel is to try to capture fundamental limits for signal quality in signal estimation. On the other hands, Shannon was interested in finding fundamental limits of signal quantity that maximize the uncertainty in mutual information using the entropy concept in noisy channel. First concern of this paper is to show that in deriving limits of Shannon's point to point fundamental channel capacity, Shannon's mutual information obtained by exploiting MMSE combiner and Wiener filter's MMSE are interelated by integro-differential equantion. Then, At the meeting point of Wiener's MMSE and Shannon's mutual information the upper bound of spectral efficiency and the lower bound of energy efficiency were computed. Choosing a proper lattice-type code of a mod-${\Lambda}$AWGN channel model and MMSE estimation of ${\alpha}$ confirmed to lead to the fundamental Shannon capacity limits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.