• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3184-3186
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• 1999

In this paper, a new structure of fully differential delay cell VCO using quadrature phase for low phase noise and high speed operation is suggested. It is realized by inserting voltage clamp circuit into input pairs of delay cells that include three-control current source having high output impedance. In this reason. this newly designed delay cell for VCO has the low power supply sensitivity so that the phase noise can be reduced. The whole characteristics of VCO were simulated by using HSPICE and SABER. Simulation results show that the phase noise of new VCO is quite small compared with conventional fully differential delay cell VCO and ring oscillator type VCO. It is also very beneficial to low power supply design because of wide tuning range.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.8-15
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• 2003

In this paper, the issue of the differential ring oscillator in designing low phase noise is linearity improvement of delay cell's load resistor. A novel differential delay cell that improves on the Maneatis load is proposed. The linearity improvement of load resistor results in lower phase noise in ring oscillator. For comparison of the phase noise characteristics, Ali Hajimiri's phase noise model is used. In order to have a low ISF(impulse sensitivity function), it is important to have a symmetry between rise time and fall time of oscillation waveform. The ISF value of ing oscillator based on the proposed delay cell is lower than that of the existing ring oscillators. Due to this result, the phase noise is improved by 2~3dBc/Hz for the same power dissipation and oscillation frequency.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Biomaterials and Biomechanics in Bioengineering
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• v.5 no.1
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• pp.51-64
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• 2020

In this study, the mathematical model that describes blood cell development in the bone marrow (i.e., hematopoiesis) has been studied via the Homotopy Perturbation Method (HPM). The results from the present work compared very well with the numerical solutions from published literature. This work has shown that the HPM is viable for solving delay differential equations born from hematopoiesis problem. The influence of the proliferating cells loss rate, time delay rate and the phase re-entry rate on the population densities of both the proliferating and resting cells were also determined through the underlined procedure.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.179-182
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• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• Kyungpook Mathematical Journal
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• v.62 no.1
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• pp.119-132
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• 2022

Virotherapy is an effective method for the treatment of cancer. The oncolytic virus specifically infects the lyse cancer cell without harming normal cells. There is a time delay between the time of interaction of the virus with the tumor cells and the time when the tumor cells become infectious and produce new virus particles. Several types of viruses are used in virotherapy and the delay varies with the type of virus. This delay can play an important role in the success of virotherapy. Our present study is to explore the impact of this delay in cancer virotherapy through a mathematical model based on delay differential equations. The partial success of virotherapy is guarenteed when one gets a stable non-trivial equilibrium with a low level of tumor cells. There exits Hopf-bifurcation by considering the delay as bifurcation parameter. We have estimated the length of delay which preserves the stability of the non-trivial equilibrium point. So when the delay is less than a threshold value, we can predict partial success of virotherapy for suitable sets of parameters. Here numerical simulations are also performed to support the analytical findings.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.7A
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• pp.569-580
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• 2012

In this paper, an enhanced initial ranging algorithm for large-cell coverage fixed wireless communication system is proposed. In typical wireless communication system such as WiBro, because a round-trip delay between a transmitter and a receiver is within one OFDM (Orthogonal Frequency Division Multiplexing) symbol duration, a frequency-domain differential correlation method is generally used. However, the conventional method cannot be applied due to an increase of a maximum time delay in large-cell system. In case of an accumulative differential method, estimation errors can occur because of frequent sign transitions. In this paper, therefore, we propose an algorithm which can estimate a total timing offset in a ranging channel structure for 15 km cell. The proposed method can improve performance by sign comparison based sign error correction rule between the estimated values and using a weighting scheme based on channel correlation, the number of accumulations, and the noise reduction effect in normalization process. Also, it can estimate the integer timing offset of symbol duration by comparing peak-powers after compensating for the fractional timing offset of symbol duration.

• Journal of applied mathematics & informatics
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• v.26 no.1_2
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• pp.355-364
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• 2008

Under pathological stress stimuli, dynamics of a biological system can be changed by alteration of several components such as functional proteins, ultimately leading to disease state. These dynamics in disease state can be modeled using differential equations in which kinetic or system parameters can be obtained from experimental data. One of the most effective ways to restore a particular disease state of biology system (i.e., cell, organ and organism) into the normal state makes optimization of the altered components usually represented by system parameters in the differential equations. There has been no such approach as far as we know. Here we show this approach with a cardiac hypertrophy model in which we obtain the existence of the optimal parameters and construct an optimal system which can be used to find the optimal parameters.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.