• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.3
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• pp.240-246
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• 1992

In the paper, the differential detection techniques of 3-h CPM signals whose modulation index is varied periodically are proposed and their error performances are analyzed. We select the modulation index sets which are proper to the differential detection and propose the differential detectors which detect symbol with 3 bits per smapling period of 3T and detect a bit per sampling period of T. Applying the nonredundant error correction circuit and viterbi algorithm to differential detection of 3-h CPM. We ascertain the error performances are improved.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.59-65
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• 1998

In this paper, a novel rail-to-rail input stage circuit with improved transconductance Is designed. Its excellent performances over whole common-mode input voltage Vcm range is demonstrated by circuit simulator HSPICE. The novel input stage circuit comprises additional 4 input transistors and 4 current sources/sinks. It maintains DC currents of signal amplifying transistors when one of the differential input stage circuits operates, but it reduces these currents to 1/4 when both differential input stage circuits operates, As a result, a operational amplifier with the novel circuit maintains nearly constant transconductance performance and unity-gain frequency in strong inversion region. The novel circuit allows an optimal frequency compensation and uniform operational amplifier performance over whole Vcm range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.685-695
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• 1997

In this paper, a new CMOS continuous-time fully-differential current-mode integrator is proposed as a basic building block of the low-voltage high frequency current-mode active filter. The proposed integrator is composed of the CMOS complementary circuit which can extend transconductance of an integrator. Therefore, the unity gain frequency which is determined by a small-signal transconductance and a MOSFET gate capacitance can be expanded by the complementary transconductance of the proposed integrator. And also the magnitude of pole and zero are increased. The unity gain frequency of the proposed integrator is increased about two times larger than that of the conventional continuous-time fully-differential integrator with NMOS-gm. These results are verified by the small signal analysis and the SPICE simulation. As an application circuit of the proposed fully-differential current-mode integrator, the three-pole Chebyshev lowpass filter is designed using 0.8.$\mu$m CMOS processing parameters. SPICE simulation predicts a 3-dB bandwidth of 148MHz and power dissipation of 4.3mW/pole for the three-pole filter with 3-V power supply.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.289-292
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• 2001

A Novel fully-differential bipolar current-controlled current amplifier(CCCA) for electrically tunable circuit design at current-mode signal processing were designed. The CCCA was consisted of fully-differential subtracter and fully-differential current gain amplifier. The simulation result shows that the CCCA has current input impedance of 0.5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100$mutextrm{A}$ to 20 ㎃. The power dissipation is 3 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.70-78
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• 2009

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.57-62
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• 1998

In this paper, tunable transconductor shows good linearity over a wide input voltage range are proposed. The proposed transconductor employ operating in the nonsaturation(ie., linear) region to improve circuit simplicity and tunability and 6.8V$\_$p-p/ wide input range. Also the circuit employ source-coupled differential pair to provide true differential input and can achieve both positive and negative transconductance values. The proposed circuits are implemented using a 1.2 $\mu\textrm{m}$ single poly double metal n-well CMOS technology. The THD characteristic of proposed circuit is less than 1% for a differential input voltage of up to 6V$\^$p-p/ when supply bias condition is V$\_$DD/=-V$\_$ss/=5V, I$\_$B/=20, 40${\mu}$A, and frequency of input signal is 1KHz.

• ETRI Journal
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• v.29 no.6
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• pp.785-793
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• 2007

In this paper, we present an integrated rail-to-rail fully differential operational transconductance amplifier (OTA) working at low-supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand-by power dissipation (lower than 0.17 mW in the rail-to-rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 ${\mu}m$), presents a 37 V/${\mu}s$ slew-rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.768-776
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• 2014

Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the $0.13{\mu}m$ CMOS process.

• Journal of IKEEE
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• v.21 no.4
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• pp.375-380
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• 2017

A differential current-to-time interval converter is presented for current mode sensors. It consists of a ramp voltage generator, a current mode sensor, a reference current source, two current-tunable Schmitt triggers, a one-shot multivibrator, and two logic gates. The design principle is to apply a ramp voltage to each input of the two current-tunable Schmitt triggers whose threshold voltages are proportional to the drain current values of the current mode sensors. A proposed circuit converts a current change in the ISFET biosensor into its equivalent pulse width change. A prototype circuit built using TSMC 0.18 nm CMOS process exhibit a conversion sensitivity amounting to $726.9{\mu}s/pH$ over pH variation range of 2-12 and a linearity error less than ${\pm}0.05%$.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.759-762
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• 1998

In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.