• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.89-93
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• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.6
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• pp.517-525
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• 2011

Differential Vibrating Accelerometer(DVA) is a small and accurate resonant device to sense the change in natural frequency in presence of acceleration input. Both mathematical modeling for the electromechanical dynamics and experimental investigation on the structural characteristics are necessary for effective designs of precision controller and high Q-factor structure. In this paper, electromechanical modeling of the resonator of DVA, electrode module, and pre-amplifier is presented. The presented method is experimentally verified by measuring the resonance frequency, effective mass, effective stiffness and Q-factor. The direct comparison of the calculated displacement and the actual pre-amplifier of DVA also indicates the effectiveness of this study.

• Journal of IKEEE
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• v.27 no.1
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• pp.53-58
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• 2023

In this paper, a Radio Frequency (RF) transformer (TF) based on LTCC (Low Temperature Co-fired Ceramic) for the output stage of differential power amplifiers is presented. Instead of using an usual L-C matching circuit, a small-sized transformer was implemented on the LTCC board and the results were verified through simulation. For reduced size and better performance, a TF using more metal layers was implemented and compared with the existing TF through simulation. As a result of comparison, the proposed TF has an area reduced by 55% and a coupling coefficient increased by 25%, and insertion loss improvement of about 0.4dB at 5GHz was confirmed.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.6-12
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• 2024

This paper presents a study on a 2.4GHz differential cascode power amplifier(PA) fabricated using a 130nm CMOS process. This PA is designed for wireless power transmission applications and consists of two differential stages with custom-designed balun transformers for single-ended output. Balun transformers are utilized not only for the output stage but also for power match-ing between each stage. Additionally, a bias circuit with temperature compensation capability is added to maintain stable bias voltage in the 2.4GHz frequency band. As a result, it achieves an output power of 21.75 dBm with a power-added efficiency(PAE) of 40.9% at TT/40℃.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.7-18
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• 2002

Single-ended differential RF circuit topologies fully utilizing complementary characteristics of both NMOS and PMOS are proposed, which have inherent advantage of both single-ended and differential circuits. Using this concept, we propose a CCPP (Complementary CMOS parallel push-pull) amplifier which has single-ended input/output with differential amplifying characteristics, leading to more than 30 dB improvement on $IIP_2$. In addition, complementary resistive mixer is also proposed, which provides not only differential IF outputs from single-ended RF input, but much better linearity as well as isolation characteristics. Experimental results using $0.35{\;}\mu\textrm{m}$ CMOS process show that, compared with conventional NMOS resistive mixer, the proposed mixer shows 15 dB better LO-to-IF isolation, 4.6 dB better $IIP_2$, and 4.5 dB better $IIP_3$performances.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.836-845
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• 2001

A Novel fully-differential bipolar current subtracter(FCS) and its application to current controlled current amplifier(CCCA) for high-accuracy current-mode signal processing were designed. To obtain full-differential current output, the FCS was symmetrically composed of two current follower with low current-input impedance. The CCCA to control output current by the bias current was consisted of the subtracter and a current gain amplifier(CGA) with single-ended current output.. The simulation result shows that the FCS has current-input impedance of 5 Ω and a good linearity. The CCCA has 3-dB cutoff frequency of 20 MHz for the range over bias current 100 $\mu$A to 20 mA. The power dissipation of the FCS and CCCA are 1.8 mW and 3 mW, respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.4 s.310
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• pp.53-59
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• 2006

This paper describes the new design technique of full wave rectifier (FWR) for precise measurement instrument and the chip implementation of this FWR circuit with measurement results. Conventional circuits have some problems of complex design and limited output range( $VDD/2{\sim}VLIIV1IT+$). Proposed FWR circuit was simply designed with two 2x1 MUXs, one high speed comparator, and one differential difference amplifier(DDA). One rail-to-rail differential difference amplifier(DDA) performs the DC level shifting to VSS and 2X amplification simultaneously, and enables the full range ($Vss{\sim}VDD$) operation. The proposed FWR circuits shows more than 50% reduction of chip area and power consumption compared to conventional one. Proposed circuit was implemented with 0.35um 1-poly 2-metal CMOS process. Core size is $150um{\times}450um$ and power dissipation is 840uW with 3.3V single supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.309-315
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• 2010

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.