• Title/Summary/Keyword: Differential amplifier

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Nondestructive Evaluation for Remanent Life of 1Cr-0.5Mo Steel by Reversible Permeability

  • Ryu, Kwon-Sang;Lee, Yun-Hee;Park, Jong-Seo;Baek, Un-Bong
    • Journal of Magnetics
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    • v.17 no.3
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    • pp.206-209
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    • 2012
  • Peak interval for reversible permeability is presented for nondestructively evaluating the remanent life of 1Cr-0.5Mo steel. The method to measure the peak interval of reversible permeability is based on the value of reversible permeability is the same as the differential value of the hysteresis loop. The measurement principle is based on the first harmonics voltage induced in a sensing coil using a lock-in amplifier tuned to a frequency of the exciting voltage. Results obtained for the peak interval of reversible permeability and Rockwell hardness on the aged samples decrease as aging time and the Larson-Miller parameter increase. We could estimate the remanent life of 1Cr-0.5Mo steel by using the relationship between the peak interval of reversible permeability and the Larson-Miller parameter, nondestructively.

Degradation Evaluation of Mechanical Property for Modified 9Cr-1Mo Steel by Reversible Permeability

  • Bong, Chung-Jong;Ryu, Kwon-Sang;Nahm, Seung-Hoon;Kim, Eun-Kyu
    • Journal of Magnetics
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    • v.16 no.1
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    • pp.42-45
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    • 2011
  • The present work studies a nondestructive evaluation of the degradation of modified 9Cr-1Mo steel using a magnetic method based on the existence of the peaks of reversible permeability (RP) in the differential magnetization around the coercive force. The apparatus is based on detection of the voltage induced in a coil using a lock-in amplifier tuned to the frequency of the AC perturbing field. Results obtained for the reversible permeability and Vickers hardness on the aged samples showed the peak interval of reversible permeability (PIRP) and Vickers hardness decrease as aging time increased. The correlation between Vickes hardness and the PIRP could be used to evaluate degradation of modified 9Cr-1Mo steel.

A Study of Low-Voltage Low-Power Bipolar Linear Transconductor and Its Application to OTA (저전압 저전력 바이폴라 선형 트랜스컨덕터와 이를 이용한 OTA에 관한 연구)

  • Shin, Hee-Jong;Chung, Won-Sup
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.37 no.1
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    • pp.40-48
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    • 2000
  • 1A novel bipolar linear transconductor and its application to operational transconductance amplifier(OTA) for low-voltage low-power signal processing is proposed. The transconductor consists of a npn differential-pair with emitter degeneration resistor and a pnp differential-pair connected to the npn differential-pair in cascade. The bias current of the pnp differential-pair is used with the output current of the npn differential-pair for wide linearity and temperature stability. The OTA consists of the linear transconductor and a translinear current cell followed by three current mirrors. The proposed transconductor has superior linearity and low-voltage low-power characteristics when compared with the conventional transconductor. The experimental results show that the transconductor with transconductance of 50 ${\mu}S$ has a linearity error of less than ${\pm}$0.06% over an input voltage range from -2V to +2V at supply voltage ${\pm}$3V. Power dissipation of the transconductor was 2.44 mW. A prototype OTA with a transconductance of 25 ${\mu}S$ has been built with bipolar transistor array. The linearity of the OTA was same as the proposed transconductor. The OTA circuit also exhibits a transconductance that is linearly dependent on a bias current varying over four decades with a sensitivity of 0.5 S/A.

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A Design of Ultra Wide Band Single-to-Differential Gain Controlled Low Noise Amplifier Using 0.18 um CMOS (0.18 um CMOS 공정을 이용한 UWB 단일 입력-차동 출력 이득 제어 저잡음 증폭기 설계)

  • Jeong, Moo-Il;Choi, Yong-Yeol;Lee, Chang-Suk
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.3
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    • pp.358-365
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    • 2008
  • A differential-gain-controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8GHz$ UWB system. In high gain mode, measurements show a differential power gain of $14.1{\sim}15.8dB,\;13.3{\sim}15dB$, respectably, an input return loss higher then 10dB, an input IP3 of -19.3 dBm, a noise figure of $4.85{\sim}5.09dB$, while consuming only 19.8 mW of power from a 1.8V DC supply. In low gain mode, measurements show a differential power gain of $-6.1{\sim}-4.2dB,\;-7.6{\sim}-5.6dB$, respectably, an input return loss higher then 10dB, an input IP3 of -1.45 dBm, a noise figure of $8.8{\sim}10.3dB$, while consuming only 5.4mW of power from a 1.8V DC supply.

A CMOS Analog Front End for a WPAN Zero-IF Receiver

  • Moon, Yeon-Kug;Seo, Hae-Moon;Park, Yong-Kuk;Won, Kwang-Ho;Lim, Seung-Ok;Kang, Jeong-Hoon;Park, Young-Choong;Yoon, Myung-Hyun;Yoo, June-Jae;Kim, Seong-Dong
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.769-772
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    • 2005
  • This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

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A Simulation-Based Analog Cell Synthesis with Improved Simulation Efficiency (시뮬레이션 효율을 향상시킨 시뮬레이션 기반의 아날로그 셀 합성)

  • 송병근;곽규달
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.8-16
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    • 1999
  • This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency For the hierarchical synthesis of analog cells we developed the sub-circuit optimizers such as current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA(operational transconductance amplifier), 2-stage OP-AMP and comparator. To reduce the time spending of the simulation-based synthesis we propose 2-stage searching scheme and simulation data reusing scheme. With those schemes the synthesis time spending of OTA was reduced from 301.05sec to 56.52sec by 81.12%. Since our synthesis system doesn't need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spending to port to other process is minimized. We synthesized OTA and 2-stage OP-AMP respectively with our approach to show its usefulness.

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A 5-Gb/s CMOS Optical Receiver with Regulated-Cascode Input Stage for 1.2V Supply (1.2V 전원전압용 RGC 입력단을 갖는 5-Gb/s CMOS 광 수신기)

  • Tak, Ji-Young;Kim, Hye-Won;Shin, Ji-Hye;Lee, Jin-Ju;Park, Sung-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.3
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    • pp.15-20
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    • 2012
  • This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.

Design of Transmitter for UWB Chaotic-OOK Communications (UWB Chaotic-OOK 통신을 위한 송신기 설계)

  • Jeong, Moo-Il;Kong, Hyo-Jin;Lee, Chang-Suk
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.3
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    • pp.384-390
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    • 2008
  • Chaotic OOK modulation method can be used in LDR(Low Data Rate) UWB systems. In this paper, UWB chaotic-OOK transmitter system is designed and verified using TSMC 0.18 um CMOS process. A transmitter system is composed of Quasi-chaotic signal generator, OOK Modulator, and driving amplifier. The traditional chaotic signal generators using analog feedback method is weak to process variation. In order to solve this problem, a quasi-chaotic signal generator using digital feedback technique is get wide band signal and OOK Modulator using T-type switching structure is used to enhance the isolation characteristic. A driving amplifier has differential to single structure to avoid an external balun for low cost communication. The measured output power spectrum of the transmitter meet the FCC regulation and the result of the modulation test at data rate of 20 Kbps, 200 Kbps, 2 Mbps, and 10 Mbps is conformed to LDR UWB system. It is shown that the transmitter in this paper can be used for the UWB chaotic-OOK system.

A Delta Modulation Method by Means of Pair Transistor Circuit (쌍트랜지스터 회로에 의한 정착변조방식)

  • 오현위
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.8 no.2
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    • pp.24-33
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    • 1971
  • A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

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Closed Integral Form Expansion for the Highly Efficient Analysis of Fiber Raman Amplifier (라만증폭기의 효율적인 성능분석을 위한 라만방정식의 적분형 전개와 수치해석 알고리즘)

  • Choi, Lark-Kwon;Park, Jae-Hyoung;Kim, Pil-Han;Park, Jong-Han;Park, Nam-Kyoo
    • Korean Journal of Optics and Photonics
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    • v.16 no.3
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    • pp.182-190
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    • 2005
  • The fiber Raman amplifier(FRA) is a distinctly advantageous technology. Due to its wider, flexible gain bandwidth, and intrinsically lower noise characteristics, FRA has become an indispensable technology of today. Various FRA modeling methods, with different levels of convergence speed and accuracy, have been proposed in order to gain valuable insights for the FRA dynamics and optimum design before real implementation. Still, all these approaches share the common platform of coupled ordinary differential equations(ODE) for the Raman equation set that must be solved along the long length of fiber propagation axis. The ODE platform has classically set the bar for achievable convergence speed, resulting exhaustive calculation efforts. In this work, we propose an alternative, highly efficient framework for FRA analysis. In treating the Raman gain as the perturbation factor in an adiabatic process, we achieved implementation of the algorithm by deriving a recursive relation for the integrals of power inside fiber with the effective length and by constructing a matrix formalism for the solution of the given FRA problem. Finally, by adiabatically turning on the Raman process in the fiber as increasing the order of iterations, the FRA solution can be obtained along the iteration axis for the whole length of fiber rather than along the fiber propagation axis, enabling faster convergence speed, at the equivalent accuracy achievable with the methods based on coupled ODEs. Performance comparison in all co-, counter-, bi-directionally pumped multi-channel FRA shows more than 102 times faster with the convergence speed of the Average power method at the same level of accuracy(relative deviation < 0.03dB).