• 한국정보통신학회논문지
• /
• 제23권10호
• /
• pp.1188-1194
• /
• 2019

유체의 흐름을 측정하는 여러 방법 중 열선 풍속 센서는 유체의 열전달에 의해 속도나 온도를 측정하는 장치로 비정상 속도 및 난류 속도 성분을 측정하는데 유용하다. 하지만 열선 풍속 센서는 외부의 환경 요인에 민감하며, 주변 온도, 습도, 신호 잡음 등에 의해 정확도가 떨어지는 단점이 있다. 이런 단점을 보완하는 방법으로 온도 보상 회로를 추가하는 기술이 나오고 있지만 가격 경쟁력을 갖출 수 없는 상황이다. 이를 해결하기 위해 본 논문에서는 온도 보상이 필요 없는 풍속 감지 센서에 대해 연구를 진행하였다. 열선식 풍속 센서는 외부 환경 요인 중에서도 주변 온도에 매우 취약하다. 주변 온도로는 전자 회로에 의한 발열의 영향이 가장 크게 미치고 있으며, 이를 개선하는 방법으로 발열체에 보조 발열체를 추가로 장착하여 보조발열체와 발열체의 일정한 온도차를 제어하는 것이다. 이와 같이 기존 기술에 비해 복잡하지 않은 방법으로 동등한 성능을 확보할 수 있다는 것을 확인할 수 있었다.

• 문화기술의 융합
• /
• 제8권6호
• /
• pp.749-755
• /
• 2022

전기는 다양한 산업에 이용되는 등 현대 사회에 있어서 필수적인 에너지이다. 그러나, 이를 다루기 위한 전자배선 상에서 발생하는 화재의 비율이 매우 높다. 본 연구에서는 다양한 회귀 모델들을 사용한 분석을 통하여 전기 회로의 온도 변화를 예측하는 시스템을 구현하였다. 이를 위해 전기 회로를 제어하는 전자 접촉기 27종을 사용한 회로상의 온도 데이터를 수집하고 수집된 온도 데이터를 이용하여 회귀 모델들을 훈련하였다. 실험에서 실제 온도와 예측온도의 차이가 평균 4℃ 정도 발생하여, 이를 통해 충분히 사용 가능한 수준의 모델을 훈련할 수 있음을 확인하였다. 이와 같은 연구 결과는 전기 회로의 온도 예측 및 화재 예방에 도움이 될 것이다.

• 한국산업정보학회논문지
• /
• 제16권5호
• /
• pp.1-8
• /
• 2011

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

• Transactions on Electrical and Electronic Materials
• /
• 제14권3호
• /
• pp.156-159
• /
• 2013

The electrical properties of ZnO nanowire field effect transistors (FETs) have been investigated depending on various diameters of nanowires. The ZnO nanowires were synthesized with an Au catalyst on c-plane $Al_2O_3$ substrates using hot-walled pulsed laser deposition (HW-PLD). The nanowire FETs are fabricated by conventional photo-lithography. The diameter of ZnO nanowires is simply controlled by changing the thickness of the Au catalyst metal, which is confirmed by FE-SEM. It has been clearly observed that the ZnO nanowires showed different diameters simply depending on the thickness of the Au catalyst. As the diameter of ZnO nanowires increased, the threshold voltage of ZnO nanowires shifted to the negative direction systematically. The results are attributed to the difference of conductive layer in the nanowires with different diameters of nanowires, which is simply controlled by changing the catalyst thickness. The results show the possibility for the simple method of the fabrication of nanowire logic circuits using enhanced and depleted mode.

• 한국전기전자재료학회논문지
• /
• 제18권9호
• /
• pp.863-869
• /
• 2005

We investigated quench characteristics of superconducting elements connected in series and parallel each other. The serial and parallel connections of superconducting elements causes a difficulty in simultaneous quench due to slight difference between their critical current densities. In other to induce simultaneous quench, we fabricated four type circuits; serially connected circuit before parallel connection, the circuit connected in parallel before serial connection, serially connected circuit before parallel connection with reactors, the circuit connected in Parallel before serial connection with reactors. We confirmed that the simultaneous quenches occurred in serial and parallel connections of superconducting elements using reactors. In addition, the power burden of superconducting elements was smaller than those of serial and parallel connections of superconducting elements without reactors.

• Journal of the Optical Society of Korea
• /
• 제15권3호
• /
• pp.283-288
• /
• 2011

In this study, a wide-band photonic crystal Y-splitter for TE modes is proposed. A triangular lattice of air holes etched in a GaAs slab is used as the platform. In order to numerically analyze the structures, plane wave expansion (PWE) and finite difference time domain (FDTD) methods are used. In comparison with the structures reported in the literature, the proposed topology has a less complexity while it provides more than 100nm bandwidth. The simplicity of the design, its high transmission ratio and its wide bandwidth makes it a suitable choice for the implementation of photonic crystal integrated circuits.

• 한국결정성장학회지
• /
• 제14권2호
• /
• pp.58-62
• /
• 2004

The shape evolution of the interface void of copper metallization for intergrated circuits under electromigration stress is modeled. A 2-dimensional finite-difference numerical method is employed for computing time evolution of the void shape driven by surface diffusion, and the electrostatic problem is solved by boundary element method. When the diffusion coefficient is isotropic, the numerical results agree well with the known case of wedge-shape void evolution. The numerical results for the anisotropic diffusion coefficient show that the initially circular void evolves to become a fatal slitlike shape when the electron wind force is large, while the shape becomes non-fatal and circular as the electron wind force decreases. The results indicate that the open circuit failure caused by slit-like void shape is far less probable to be observed for copper metallization under a normal electromigration stress condition.

• 한국전기전자재료학회논문지
• /
• 제15권10호
• /
• pp.844-850
• /
• 2002

Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.

• 전자공학회논문지D
• /
• 제35D권4호
• /
• pp.84-92
• /
• 1998

A program was developed to analyze the electrical characteristics and harmonic distrotion in a two-dimensional silicon BJT. The finite difference equations of the small signal and its second and thired harmonics for basic semiconductor equations are formulated treating the nonlinearity and time dependence with Volterra series and Taylor series. The soluations for three sets of simultaneous equations were obtained sequantially by a decoupled iteration method and each set was solved by a modified Stone's algorithm. Distortion magins and ac parameters such as input impedance and current gains are calculated with frequency and load resistance as parameters. The distortion margin vs. load resistancecurves show cancellation minima when the pahse of output voltage shifts. It is shown that the distortionof small signal characteristics can be reduced by reducing the base width, increasing the emitter stripe length and reducing the collector epitaxial layer doping concentration in the silicon BJT structure. The simulation program called TRADAP can be used for the design and optimization of transistors and circuits as well as for the calculation of small signal and distortion solutions.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 1995년도 Proceedings of the Korea Automation Control Conference, 10th (KACC); Seoul, Korea; 23-25 Oct. 1995
• /
• pp.236-239
• /
• 1995

It is useful to simulate the human visual function for the purpose of image-processing. In this study, the hardware of the spatial filter with the sensitivity of lateral inhibition is realized by the combination of optical parts with electronic circuits. The diffused film with the characteristics of Gaussian type is prepared as a spatial filter. An object's image is convoluted with the spatial filter. From the difference of the convoluted images, the zero-cross position is detected at video rate. The edge of object is extracted in real-time by the use of this equipment. The resolution of edge changes with the value of the standard deviation of diffused film. In addition, it is possible to extract a directional edge selectively when the spatial filter with directional selectivity is used instead of Gaussian type of spatial filter.