• 대한기계학회논문집
• /
• 제10권5호
• /
• pp.653-660
• /
• 1986

본 논문에서는 단일 노치가 있는 봉의 소성굽힘, 밀폐형단조, 4각형블록의 압 축, 2차원 절삭가공 및 평면변형 후방추출 등 평면변형 성형문제에 대해서 공구와 소 재사이에 일정한 마찰응역이 작용한다는 가정하에 운동학적 가용속도장으로 구한 상 계해와 동일한 변형모델을 사용하여 힘평형법으로 구한 상계해를 비교.검토하여 2가지 접근법으로 구한 상계해가 동일함을 입증하였다.

• 한국소성가공학회:학술대회논문집
• /
• 한국소성가공학회 1994년도 춘계학술대회 논문집
• /
• pp.63-70
• /
• 1994

An upper bound elemental technique(UBET) is applied to predict forging load and die-cavity filling for non-axisymmetric ring forging. The finial product is divided into three different deformation regions. That is axisymmetric part in corner, lateral plane-strain part and shear deformation on boundaries between them. The plane-strain and axisymmetric part are combinded by building block method. Also the total energy is computered through combination of three deformation part. Experiments have been carried out with pure plasticine billets at room temperature. The theoretical predictions of the forging load and the flow pattern are in good agreement with the experimental results.

• 한국주조공학회지
• /
• 제43권1호
• /
• pp.3-10
• /
• 2023

본 연구는 다이캐스팅 과정 중 발생될 수 있는 비철금속 가공품 내부의 기공 결함을 검출할 수 있는 기술 개발을 위해 진행되었다. 해당 연구를 통해 제품 내부에 발생 가능한 기공을 사전에 검출하여 불량 생산품의 유통을 사전에 차단하고 나아가 유통된 제품의 파손으로 발생 가능한 손실을 감소시키는데 기여하고자 한다.

• 한국정밀공학회지
• /
• 제18권5호
• /
• pp.57-64
• /
• 2001

The high speed in the wire-drawing process to meet the demands for the increased productivity has a great effect on the heat generated due to plastic deformation and friction between the wire and the drawing dies. During the high carbon steel wire drawing process, the temperature rise gives a great influence to the fracture of wire. In this paper, to control the temperature rise in the wire after the deformation through the drawing die, the calculation method of the wire temperature, which includes the temperature rise in the deformation zone as well as the temperature drop in the block considering the heat transfer among the wire, cooling water and surrounding air, is proposed. These calculated results of the wire temperature at the inlet and exit of the drawing die at each pass are compared with the measured wire temperatures and verified its efficiency. So, using the program to predict the wire temperature, the isothermal pass schedule program was developed. By applying this isothermal pass schedule program to the conventional process condition, a new isothermal pass schedule is redesigned through all passes. As a result, the possibility of wire fracture could be considerably reduced and the productivity of final product could be more increased than before.

• Design & Manufacturing
• /
• 제10권1호
• /
• pp.41-45
• /
• 2016

Electrical equipment in factories, buildings, etc. with the development of the industry has become a large capacity. By the development, electric load also become diversified and there is also highly functional requirements being electrical equipment. Particularly in the small and medium-sized circuit breakers, tend to preferentially consider the economy stands out and improvements in safety, ease of mounting and connection through the modularity of the basic dimensions compact and cost to block expansion of the scope of the development of capacity, etc. The product having a competitive has been strongly required. In order to implement the circuit breakers of breaking capacity and compact at the same time taking into account the economic development of this technology applied to the current-limiting mechanism is essential budget or the current limiting mechanism is currently available mechanisms applicable to small and medium-sized frame (frame) can not do it. In this paper, at the same time satisfying the economic efficiency, by minimizing the load force of the moving contactor (moving contactor) to be applied to small and medium frame other hand to secure the economical efficiency without using high speed contact parting acceleration of the moving contactor conventional current-limiting mechanism, and to develop a current-limiting mechanism that can be satisfied with the same or higher performance to meet the needs of the market.

• 구강회복응용과학지
• /
• 제36권2호
• /
• pp.61-69
• /
• 2020

목적: 하악 제2소구치와 제2대구치를 지대치로 한 지르코니아 고정성 국소의치에서 지대치 간 거리가 파절저항성에 미치는 영향을 조사하였다. 연구 재료 및 방법: Cameleon S zirconia block과 Luxen S2 zirconia block으로 각 재료별 지대치 간 거리를 달리 하여 CS군과 S2군으로 나누어 표기하였으며, 소결된 지르코니아 고정성 국소의치를 임시접착시멘트를 이용하여 에폭시 레진 다이에 합착하였다. 이후, 가공치 교합면에 직경 6 mm 강철구를 위치시켜 로드셀 5.0 kN의 universal testing machine에서 크로스 헤드 속도 1.0 mm/min로 압력을 가하여 파절저항성을 측정하였다. 결과: 지르코니아 고정성 국소의치의 파절저항성은 지대치 간 거리에 큰 영향을 받지 않았다. CS군에서 지대치 간 거리가 15 mm인 경우가 13 mm와 17 mm인 경우보다 파절저항성이 유의하게 높았다(P < 0.05). S2군에서는 파절저항성이 세 군 간에 유의한 차이가 없었다(P > 0.05). 결론: 하악 제2소구치와 제2대구치를 지대치로 한 지르코니아 고정성 국소의치에서 지대치 간 거리는 지르코니아의 종류에 따라 파절저항성에 영향을 줄 수 있다.

• 전기전자학회논문지
• /
• 제2권1호
• /
• pp.34-41
• /
• 1998

자기 띠 저장 시스템에서 데이터를 저장하고 복원할 수 있는 칩을 구현하였다. 구현된 칩은 아날로그 회로와 디지털 회로가 한 칩안에 같이 내장되어 있으며 F/2F 인코딩과 디코딩을 동시에 지원한다. 아날로그 부분은 초단 앰프, 첨두치 검출기, 비교기, 기준전압 생성회로 등으로 구현 되었으며 디지탈 회로 부분은 기준 윈도우 신호 발생부, F/2F 신호 길이를 측정하는 up/down 계수부, 비트 에러 검출부 및 기타 제어(control) 회로 등을 포함한다. 검출되는 신호특성을 파악하여 아날로그 회로부 설계를 최적화 함으로써 기존의 시스템에서 흔히 쓰이는 AGC(automatic gain control) 회로를 제거하였다. 또 일정한 비트의 길이를 초과한 파손 비트 또는 다분할로 파손된 비트 등을 감지한 경우 신속하게 기준 비트를 재 설정함으로서 데이터의 오인식을 없애주는 회로를 제안하였다. 제안된 회로는 $0.8{\mu}m$ CMOS N-well 일반 공정을 이용하여 구현 되었으며 3.3 V에서 부터 7.5 V의 공급 전압 범위에서 동작하도록 설계 되었다. 5 V의 전원 공급시 약 8 mW의 소모 전력을 보여 주고 있으며 칩 면적은 패드를 포함하여 $3.04mm^2(1.6mm{\times}1.9mm)$이다.

• 한국CDE학회논문집
• /
• 제8권4호
• /
• pp.254-261
• /
• 2003

In mold and die shops, NC machining process mainly affects the quality of the machined surface and the manufacturing time of molds and dies. The estimation of NC machining time is a prerequisite to measure the machining productivity and to generate a process schedule, which generally includes the process sequence and the completion time of each process. It is required to take into account dynamic characteristics in the estimation, such as the ac/deceleration of NC machine controllers. Intensive observations at start and end points of NC blocks show that a minimum feedrate, a key variable in a machining time model, has a close relation to a block distance, an angle between blocks, and a command feedrate. Thus, this study addresses regression models for the minimum feedrate estimation on short and long NC blocks considering these parameters. Furthermore, machining time estimation models by the four types of feedrate behaviors are suggested based on the estimated minimum feedrate. To show the validity of the proposed machining time model, the study compares the estimated with the actual machining time in the sculptured surface machining of several mold dies.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권4호
• /
• pp.211-216
• /
• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.499-500
• /
• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.