• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.1-6
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• 2013

3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D IC technology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging. However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturing yield, and device test. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling system has been reviewed as one of device cooling methods for the next generation thermal management.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.27-30
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• 2003

In this paper a new approach of digitalized ‘Takbon’ is introduced. By image signal processing, the letters which were written on stones can be deciphered. Epigraphic letter is detected by digital image device, digital camera. The two dimensional digital image is preprocessed because of sensor noise and detective turbulence. Color image is transformed into grey level. The letter image is analyzed in time/frequency domain. By the resultant analysis data decisive functions are calculated. Signal Processing techniques, such as scaling, clipping, digital negative, high/low filter, morphology and so on, provide algorithms that can extract letter from stones.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.89.1-89
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• 2001

Measurement of complex surfaces without touching is desirable in several fields. This arises mainly for measurement of complex surfaces including those surfaces that deform during touch. Our research presented in this paper describes the use of a 3D digitizer for scanning 3D objects. The use of such a device, in addition to proper calibration, requires proper scaling in all three dimensions. We propose measurement techniques to measure various aspects of the surface circumference, area and volume. We also present experiments from using a 3D Minolta digitizer for measuring 3D human heads.

• Korean Journal of Crystallography
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• v.16 no.2
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.19-19
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• 2008

We investigated the programmable memory characteristics of nanoparticle-based memory devices based on the elementary metal nanoparticles (Co and Au) and their binary mixture synthesized by a micellar route to ordered arrays of metal nanoparticles as charge trapping layers. According to the metal nanoparticle species quite different programming/erasing efficiencies were observed, resulting in the tunable memory characteristics at the same programming/erasing bias conditions. This finding will be a good implication for further device scaling and novel device applications since most processes are based on the conventional semiconductor processes.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1042-1045
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• 2002

The scaling of device dimension and supply voltage with high performance and reliability has been the main subject in the evolution of VLSI technology, The MOSFET structures become susceptible to high field related reliability problems such as hot-electron induced device degradation and dielectric breakdown. HLDBD(HLD Buffered Deposition) is used to decrease junction electric field in this paper. Also we compared the hot carrier characteristics of HLDBD and conventional.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• Transactions on Electrical and Electronic Materials
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• v.6 no.1
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.