• Title/Summary/Keyword: Device Wafer

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Plasma 공정에서 Gas Purge를 이용한 미세 Particle 제어방법 연구

  • Kim, Tae-Rang;Bang, Jin-Yeong;Gang, Tae-Gyun;Choe, Chang-Won;Yun, Tae-Yang
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.196.1-196.1
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    • 2013
  • 반도체의 device design rule이 shrink 됨에 따라 공정이 난이도가 높아지고 이에 따른 관리가 어려워지고 있다. 특히 미세 particle에 대한 제어의 필요성은 보다 커졌다. 진공 chamber 발생하는 미세 particle의 주요 원인으로는 공정 중 발생한 polymer, chamber 내 부품의 식각 및 스퍼터링에 의한 부산물 등이 있다. Plasma 공정 도중 발생한 particle은 plasma 내 전자에 의해 대전되어 음의 전하량을 가지게 된다. 음의 전하량을 가진 particle은 plasma와 wafer의 경계면에서 형성되는 sheath 때문에 wafer에 도달하지 못하고 plasma 내에 부유하게 된다. 이러한 particle은 plasma가 꺼지게 되면 sheath가 사라지면서 wafer에 도달하게 되고 wafer의 오염을 유발하게 되고 생산 수율을 저하시키는 요인이 된다. 이러한 이유로 최근 plasma 공정에서는 공정 중 발생하는 부유성 particle에 대한 관리가 중요해졌다. 이를 관리하기 위해 plasma를 끄기 전 부유성 particle을 제거하는 방안을 고안하고 평가를 진행하였다. 공정이 끝나고 plasma가 꺼지기 전 plasma를 유지하여 부유성 particle이 wafer에 도달하지 못하는 상태에서 gas purge를 실시한다. 이러한 과정 후 plasma를 끄게 되면 부유성 particle이 wafer에 도달하는 것을 감소시키게 된다. 이번 평가를 통해 부유성 particle에 대해서 대략 20%의 감소 효과를 볼 수 있었다. 이를 토대로 향후 조건 최적화 후 적용 시 particle 감소뿐 만 아니라 수율 향상에도 기여할 수 있을 것이라 기대된다.

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The New Generation Laser Dicing Technology for Ultra Thin Si wafer

  • Kumagai, Masayoshi;Uchiyama, N.;Atsumi, K.;Fukumitsu, K.;Ohmura, E.;Morita, H.
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2006.10a
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    • pp.125-134
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    • 2006
  • Process & mechanism $\blacklozenge$ The process consists from two steps which are laser processing step and separation steop. $\blacklozenge$ The wavelength of laser beam is transmissible wavelength for the wafer. However, inside of Si wafer is processed due to temperature dependence of optical absorption coefficient Advantage & Application $\blacklozenge$ Advantages are high speed dicing, no debris contaminants, completely dry process, etc. $\blacklozenge$ The cutting edges were fine, The lifetime and endurances did not degrade the device characteristics $\blacklozenge$ A separation of a wafer with DAF was introduced as an application for SiP

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Statistical Analysis on Critical Dimension Variation for a Semiconductor Fabrication Process (반도체 제조공정의 Critical Dimension 변동에 대한 통계적 분석)

  • Park, Sung-Min;Lee, Jeong-In;Kim, Byeong-Yun;Oh, Young-Sun
    • IE interfaces
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    • v.16 no.3
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    • pp.344-351
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    • 2003
  • Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

Zeta-potential in CMP process of sapphire wafer on poly-urethane pad (폴리우레탄 패드를 이용한 기계-화학 연마공정에서 파이어 웨이퍼 표면 전위)

  • Hwang, Sung-Won;Shin, Gwi-Su;Kim, Keun-Joo;Suh, Nam-Sup
    • Proceedings of the KSME Conference
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    • 2003.11a
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    • pp.1816-1821
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    • 2003
  • The sapphire wafer for blue light emitting device was manufactured by the implementation of the chemical and mechanical polishing process. The surface polishing of crystalline sapphire wafer was characterized by zeta potential measurement. The reduction process with the alkali slurry provides the surface chemical reaction with sapphire atoms. The poly-urethane pad also provides the frictional force to take out the chemically-reacted surface layers. The surface roughness was measured by the atomic force microscope and the crystalline quality was characterized by the double crystal X -ray diffraction analysis.

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GaN-based Ultraviolet Passive Pixel Sensor for UV Imager

  • Lee, Chang-Ju;Hahm, Sung-Ho;Park, Hongsik
    • Journal of Sensor Science and Technology
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    • v.28 no.3
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    • pp.152-156
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    • 2019
  • An ultraviolet (UV) image sensor is an extremely important optoelectronic device used in scientific and medical applications because it can detect images that cannot be obtained using visible or infrared image sensors. Because photodetectors and transistors are based on different materials, conventional UV imaging devices, which have a hybrid-type structure, require additional complex processes such as a backside etching of a GaN epi-wafer and a wafer-to-wafer bonding for the fabrication of the image sensors. In this study, we developed a monolithic GaN UV passive pixel sensor (PPS) by integrating a GaN-based Schottky-barrier type transistor and a GaN UV photodetector on a wafer. Both individual devices show good electrical and photoresponse characteristics, and the fabricated UV PPS was successfully operated under UV irradiation conditions with a high on/off extinction ratio of as high as $10^3$. This integration technique of a single pixel sensor will be a breakthrough for the development of GaN-based optoelectronic integrated circuits.

A Study on Kinematical Modeling and Analysis of Double Side Wafer Polishing Process (실리콘 웨이퍼 양면 연마 공정의 기구학적 모델링과 해석에 관한 연구)

  • Lee, Sang-Jik;Jeong, Suk-Hoon;Lee, Hyun-Seop;Park, Sun-Joon;Kim, Young-Min;Jeong, Hae-Do
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.485-485
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    • 2009
  • Double side polishing process has been used for various industrial applications, such as polishing of semiconductor substrates and flat panel display glasses. In wafer manufacturing, double side polishing process is applied to improve wafer flatness and to minimize particle generation from wafers in device manufacturing processes, which is recognized as one of the most important processes. Whereas the kinematical modeling and analysis results of single side polishing, extensively used for chemical-mechanical polishing (CMP) in device manufacturing, are well investigated, the studies in conjunction with double side polishing are barely carried out, due to the complication of polishing system and the uncertainty of wafer motion in the carrier. This paper suggests the derivation of kinematical model with consideration of carrier and wafer motion in double side polishing, and then presents the effect of kinematical parameters on material removal amount and its non-uniformity. The kinematical analysis results help to understand the double side polishing process and to control the polishing results.

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The Magnetic Sensor with Lateral Field Emitter Arrays (평면구조의 전계방출형 자기 센서)

  • 남명우;김시헌;남태철
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1995.05a
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    • pp.124-128
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    • 1995
  • We have fabricated the vacuum magnetic device with a lateral field emitter arrays constructed on n-Si wafer, and investigated its magnetic characteristics. The device is consited to tip-arrayed emitter. gate and split-anode, The fabricated vacuum magnetic device has showed a good linearity of magnetic field and a high sensitivity compared with the conventional semiconductor magnetic device.

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Micromachinng and Fabrication of Thin Filmes for MEMS-infrarad Detectors

  • Hoang, Geun-Chang;Yom, Snag-Seop;Park, Heung-Woo;Park, Yun-Kwon;Ju, Byeong-Kwon;Oh, Young-Jei;Lee, Jong-Hoon;Moonkyo Chung;Suh, Sang-Hee
    • The Korean Journal of Ceramics
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    • v.7 no.1
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    • pp.36-40
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    • 2001
  • In order to fabricate uncooled IR sensors for pyroelectric applications, multilayered thin films of Pt/PbTiO$_3$/Pt/Ti/Si$_3$N$_4$/SiO$_2$/Si and thermally isolating membrane structures of square-shaped/cantilevers-shaped microstructures were prepared. Cavity was also fabricated via direct silicon wafer bonding and etching technique. Metallic Pt layer was deposited by ion beam sputtering while PbTiO$_3$ thin films were prepared by sol-gel technique. Micromachining technology was used to fabricate microstructured-membrane detectors. In order to avoid a difficulty of etching active layers, silicon-nitride membrane structure was fabricated through the direct bonding and etching of the silicon wafer. Although multilayered thin film deposition and device fabrications were processed independently, these could b integrated to make IR micro-sensor devices.

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Silicon Intrinsic Gettering Technology: Understanding and Practice (실리콘 Intrinsic Gettering 기술의 이해와 응용)

  • Choe Kwang Su
    • Korean Journal of Materials Research
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    • v.14 no.1
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    • pp.9-12
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    • 2004
  • Metallic impurities, such as Fe, Cu, and Au, become generation and recombination centers for minority carriers when combined with oxide precipitates or silicon self-interstitial clusters. As these centers may cause leakage and discharge in silicon devices, their prevention through gettering of the metallic impurities is an important issue. In this article, key aspects of intrinsic gettering, such as oxygen control, wafer cleaning, device area denudation, and bulk oxygen precipitation are discussed, and a practical method of implementing intrinsic gettering is outlined.

RF-MEMS 소자를 위한 저손실 웨이퍼 레벨 패키징

  • 박윤권;이덕중;박흥우;송인상;김정우;송기무;박정호;김철주;주병권
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.11a
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    • pp.124-128
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    • 2001
  • We apply for the first time a low cost and loss wafer level packaging technology for RF-MEMS device. The proposed structure was simulated by finite element method (FEM) tool (HFSS of Ansoft). S-parameter measured of the package shows the return loss (S11) of 20dB and the insertion loss (S21) of 0.05dB.

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