• Proceedings of the Korean Operations and Management Science Society Conference
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• 2002.05a
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• pp.285-292
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• 2002

A cluster tool for semiconductor manufacturing is an integrated device that consists of several single wafer processing modules and a wafer transport module based on a robot. The distributed module controllers are integrated by an inter-module communication network and coordinated by a centralized controller, called a cluster tool controller (CTC). Since the CTC monitors and coordinates the distributed complex module controllers for advanced process control, complex commuication messaging and services between the CTC and the module controllers are required. A SEMI standard, CTMC(Cluster Tool Module Communication), specifies application-level communication service requirements for inter-module communication. We propose the use of high-level fieldbuses, for instance. PROFIBUS-FMS, for implementing CTMC since the high-level fieldbuses are well suited for complex real-time distributed manufacturing control applications. We present a way of implementing CTMC using PROFIBUS-FMS as the communication enabler. We first propose improvements of a key object of CTMC for material transfer and the part transfer protocol to meet the functional requirements of modem advanced cluster tools. We also discuss mapping objects and services of CTMC to PROFIBUS-FMS communication objects and services. Finally, we explain how to implement the mappings.

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.3
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• pp.111-116
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• 2004

The Ni/SiC Schottky diode was fabricated with the $\alpha$-SiC thin film grown by the ICP-CVD method on a (111) Si wafer. $\alpha$-SiC film has been grown on a carbonized Si layer in which the Si surface was chemically converted to a very thin SiC layer achieved using an ICP-CVD method at $700^{\circ}C$. To reduce defects between the Si and $\alpha$-SiC, the surface of the Si wafer was slightly carbonized. The film characteristics of $\alpha$-SiC were investigated by employing TEM (Transmission Electron Microscopy) and FT-IR (Fourier Transform Infrared Spectroscopy). Sputterd Ni thin film was used as the anode metal. The boundary status of the Ni/SiC contact was investigated by AES (Auger Electron Spectroscopy) as a function of the annealing temperature. It is shown that the ohmic contact could be acquired beyond a 100$0^{\circ}C$ annealing temperature. The forward voltage drop at 100A/cm was I.0V. The breakdown voltage of the Ni/$\alpha$-SiC Schottky diode was 545 V, which is five times larger than the ideal breakdown voltage of the silicon device. As well, the dependence of barrier height on temperature was observed. The barrier height from C- V characteristics was higher than those from I-V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.208-211
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• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• Proceedings of the KAIS Fall Conference
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• 2010.05a
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• pp.108-112
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• 2010

Confocal Imaging System is an essential machine for a wide range of inspection wafer. For concurrent and fast acquiring the image data of four channels, the new image acquisition system used the protocol of camera-link standard with the full mode of configuration in interconnection with a frame grabber integrated in a computer, which is popularly used for many cameras, so the programming environment of image processing is optional such as Visual C++, Matlab. In addition, many conventional methods were coordinately used for contribution to build the high quality of images for precise processing analog signals of PhotoMutiplier Tubes(PMTs), accurate control of scanning device, sensitivity of PMTs, and laser source. The prototype of new image acquisition system, could meet the goal of development, it is used in LSCM for high content screening to investigation the processes of elements of living specimens at the same time by simultaneous grab image data on 4 PMTs channels.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.571-572
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• 2006

Tungsten CMP needs interconnect of semiconductor device ULSI chip and metal plug formation, CMP technology is essential indispensable method for local planarization. This Slurry development also for tungsten CMP is important, slurry of metal wiring material that is used present is depending real condition abroad. It is target that this research makes slurry of efficiency that overmatch slurry that is such than existing because focus and use colloidal silica by abrasive particle to internal production technology development. Compared selectivity of slurry that is developed with competitor slurry using 8" tungsten wafer and 8" oxide wafer in this experiment. And removal rate measures about density change of $H_2O_2$ and Fe particle. Also, corrosion potential and current density measure about Fe ion and Fe particle. As a result, selectivity find 83:1, and expressed similar removal rate and corrosion potential and current density value comparing with competitor slurry.

• Journal of Practical Engineering Education
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• v.10 no.2
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• pp.125-129
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• 2018

This paper is about the numerical analysis on optimized internal flow of LTP furnace and uniformity of temperature. The LTP Furnace is the device that generates heat by electricity. And performs an annealing function for annealing the silicon wafer in the pre-semiconductor manufacturing process. Especially, the maximum temperature inside the chamber is maintained at a high temperature of about $400^{\circ}C$ to strengthen the wafer. When the process is completed at high temperature, the operation is repeated to reduce the temperature through the heat exchanger and carry it out. From this analysis, the ultimate goal is to derive the optimum design of the insulation volume supply/exhaust structure of the chamber through the flow analysis of the LTPS furnace. And to find cases for curriculum development.

• Applied Microscopy
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• v.52
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.4
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• pp.75-80
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• 2013

Single crystal sapphire being used in high technology industry is a brittle material with a high hardness and excellent physical properties. ELID(Electrolytic In-Process Dressing) grinding technology was applied to material removal machining process of single crystal sapphire wafer. Ultrasonic vibration which added to material using ultrasonic table was adopted to efficient ELID grinding of sapphire materials. The evaluation of the ground surface of single crystal sapphire wafer was carried out by means of surface measuring by using AFM(Atomic Force Microscope), surface roughness tester and optical microscope device. As the results of experiment, it was shown that more efficient grinding was conducted when using ultrasonic table. In case of using #170 grinding wheel, surface roughness of ELID ground specimen in using ultrasonic table was superior to ELID ground specimen without ultrasonic table. However, In case of using #2000 grinding wheel, surface roughness of ELID ground specimen in using ultrasonic table was inferior to ELID ground specimen without ultrasonic table.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.438-439
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• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.