• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1921-1923
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• 2001

In this work, an array of resistance temperature detector(RTD) was fabricated inside the microchannel in order to investigate in-situ flow characteristics. A rectangular straight microchannel, integrated with RTD's for temperature sensing and a heat source for generating the temperature gradient along the channel. were fabricated with the dimension of $200{\mu}m(W){\times}{\mu}m(D){\times}$48mm(L), while RTD measured precise temperatures at the inside-channel wall. 4" $525{\pm}25{\mu}m$ thick P-type <100> Si wafer was used as a substrate. For the fabrication of RTDs. 5300$\AA$ thick Pt/Ti layer was sputtered on a Pyrex glass wafer. Finally, glass wafer was bonded with Si wafer by anodic bonding, therefore RTD was located inside the microchannel. The temperature distribution inside the fabricated microchannel was obtained from 4 point probe measurements and Dl water is used as a working fluid. Temperature distribution inside the microchannel was measured as a function of mass flow rate and heat flux. As a result, precise temperatures inside the microchannel could be obtained. In conclusion, this novel temperature distribution measurement system will be very useful to the accurate analysis of the flow characteristics in the microchannel.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.881-885
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• 2004

We report a method for making a device on which semi-conducting single-walled carbon nanotubes are attached selectively between two metal electrodes. This method is divided two processes. First we can connect a rope of single-walled carbon nanotubes(SWNTs) between two electrodes using the electric field. But a SWNTs' rope obtained by the first process was composed of a few of metallic and semi-conducting SWNTs together. The second process is to burn the metallic and semi-conducting nanotubes through applying a voltage. As a result, we can obtain a semi-conducting SWNT device. To make the patterned electrodes, we deposited $SiO_2$(150nm) on a wafer. After then, we made a patterned samples with Ti(200 $\AA$)/Au(300$\AA$). We empirically obtained a electric condition 0.66 $V_{pp}$ /${\mu}{\textrm}{m}$@5MHz. From this result, we verified that most of current go through the metallic nanotubes in this device. When we apply DC voltage between two electrodes, the metallic carbon nanotubes are burnt. Finally, we can obtain a semi-conducting nanotube device which we desire to make. We got the I-V characteristic graph which has shown the semi-conducting property. We hope to apply to the various applications using this selective semi-conducting carbon nanotube deposition method.ethod.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1497-1499
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• 2000

We give pressure stimulation into organic thin films and then manufacture a device under the accumulation condition that the state surface pressure is 30 [mN/m]. LB layers of Arac. acid deposited by LB method were deposited onto y-type silicon wafer as y-type film. In processing of a device manufacture. we can see the process is good from the change of a surface pressure for organic thin films and transfer ratio of area per molecule. The structure of manufactured device is Au/arachidic acid/Al. the number of accumulated layers are 9$\sim$21. Also. we then examined of the MIM device by means of I-V. The I-V characteristic of the device is measured from -3 to +3[V]. The insulation property of a thin film is better as the distance between electrodes is larger.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.27-36
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• 2001

In this paper, micromachined millimeter-wave cavity resonators ar presented. One-port and two-port cavity resonators at Ka-band are designed using 3D design software, HP $HFSS^{TM}$ ver. 5.5 Cavity resonators are fabricated on Si substrate, which is etched down for the cavity, bonded with a Quartz wafer in which metal patterns for the feeding line coupling slot are formed. One-port resonator shows the resonant frequency of 39.34 GHz, the return loss of 14.5 dB, and the loaded $Q(Q_{L})$ of 150. Two-port cavity resonator shows the resonant frequency of 39 GHz, the insertion and return losses of 4.6dB and 19,9dB, the loaded($Q_{L}$) and unloaded $Q(Q_{U})$) of 44.3 and 107, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1339-1343
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• 2004

This paper presents a development of the control algorithm and Pick & Placer. The Pick & Placer provides a powerful multi-task system that includes both graphical and remote interface. Users can easily set up sorting parameters and record important data including wafer number, data, and operator information. This System sets up a dustproof device and massively machined components to provide an extremely stable sorting environment. Precise resolution and accuracy result from using machine vision, a pneumatic slide drive and close -looped positioning.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1103-1107
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• 2005

Single-crystal silicon thin films on glass (SOG) and on fused-quartz (SOQ) were prepared using wafer bonding and hydrogen-induced layer transfer. Thinfilm transistors (TFTs) were subsequently fabricated. The high-temperature processed SOQ TFTs show better device performance than the low-temperature processed SOG TFTs. Tensile and compressive strain was measured respectively on SOQ and SOG. Consistent with the tensile strain, enhanced electron effective mobility was measured on the SOQ TFTs.