• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.223-231
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• 2015

As smartphones support a variety of applications and their memory demand keeps increasing, the design of an efficient memory management policy is becoming increasingly important. Meanwhile, as nonvolatile memory (NVM) technologies such as PCM and STT-MRAM have emerged as new memory media of smartphones, characterizing memory references for NVM-based smartphone memory systems is needed. For the deep understanding of memory access features in smartphones, this paper performs comprehensive analysis of memory references for various smartphone applications. We first analyze the temporal locality and frequency of memory reference behaviors to quantify the effects of the two properties with respect to the re-reference likelihood of pages. We also analyze the skewed popularity of memory references and model it as a Zipf-like distribution. We expect that the result of this study will be a good guidance to design an efficient memory management policy for future smartphones.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.499-501
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• 2003

As semiconductor memory becomes cheaper, the memory capacity of computer system is increasing. Therefore computer system has sufficient memory for a plentiful spatial data. With emerging spatial application required high performance, this paper presents a GIS database system in main memory. Memory residence can provide both functionality and performance for a database management system. This paper describes design of DBMS for storing, querying, managing and analyzing for spatial and non-spatial data in main-memory. This memory resident GIS DBMS supports SQL for spatial query, spatial data model, spatial index and interface for GIS tool or applications.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.39-42
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• 2001

This paper proposes the design technique of memory sparing to overcome memory hard error Memory Sparing is used to increase the reliability and availability of commercial, military and space computer such as a Data Server, Communication Server, Flight Computer in airplane and On-Board Computer in spacecraft. But the documents about this technique are rare and hard to find. This paper has some useful information about memory error correction and memory error management.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.719-722
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• 1998

Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.167-168
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• 2007

Design Rule이 작아짐에 따라 Transistor performance 향상을 위한 여러 방안중 SEG 공정이 적용되고 있으며 이에 따른 Transistor 특성 연구 결과이다. SEG공정 적용시 SEG Profile에 따라 Transistor의 Short Channel Effect 열화가 발생하였고 그 원인은 Sidewall Facet발생으로 추정되며 이를 개선시 Tr 특성이 개선됨을 확인하였다.

• Korean Management Science Review
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• v.26 no.1
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• pp.171-182
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• 2009

We consider the inventory replenishment problem and the vehicle routing problem simultaneously in the vending machine operation. This problem is known as the inventory routing problem. We design a memory cell in the clonal selection algorithm. The memory cell store the best solution of previous solved problem and use an initial solution for next problem. In general, the other clonal selection algorithm used memory cell for reserving the best solution in current problem. Experiments are performed for testing efficiency of the memory cell in demand uncertainty. Experiment result shows that the solution quality of our algorithm is similar to general clonal selection algorithm and the calculations time is reduced by 20% when the demand uncertainty is less than 30%.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.4
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• pp.389-394
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• 2010

This paper describes the conceptual design of mass memory unit for high speed data processing and mass memory management in the STSAT-3 compared to that of STSAT-2. The FPGA directly controls the data receiving from two payloads with the maximum 100Mbps speed and 32Gb mass memory management to satisfy these requirements. We used SRAM-based FPGA from XILINX having fast operating speed and large logic cells. Therefore, the Triple Modular Redundancy(TMR) and configuration memory scrubbing techniques will also be used to protect FPGA from Single Event Upset(SEU) in space.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.185-190
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• 2007

The necessity of error test module is increasing as development of embedded Linux device driver. This paper proposes the basic concept of freed memory error test module in the Linux device driver and designs error test module. The USB device driver is designed for freed memory error test module. I insert the test code to verify the USB device driver. I test the suggested error test module for the USB storage device driver. I experiment error test in this module.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.1
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• pp.71-76
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• 2023

Recently, a memory management strategy that utilizes read and write references separately is attracting attention. This is due to the emergence of new storage media with asymmetric read/write latencies and different read/write access characteristics of software. Existing research assumes that operating systems can differentiate between read/write references that occur on each memory page, but most memory architectures do not support a way to distinguish them. Unlike previous studies, this paper proposes a software method that reflects the read/write characteristics of page references by utilizing the reference and modified bits of each page. Simulations show that the proposed policy has almost similar effects to existing studies with hardware support.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.