• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.433-442
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• 1995

This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.140-148
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• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1411-1417
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• 2014

An MPEG-2 AAC Huffman decoding method based on the fixed length compacted codeword tables, where each codeword can contain multiple number of Huffman codes, was proposed. The proposed method enhances the searching efficiency by finding multiple symbols in a single search, i.e., a direct memory reading of the compacted codeword table. The memory usage is significantly saved by separately handling the Huffman codes that exceed the length of the compacted codewords. The trade-off relation between the computational complexity and the amount of memory usage was analytically derived to find the proper codeword length of the compacted codewords for the design of MPEG-2 AAC decoder. To validate the proposed algorithm, its performance was experimentally evaluated with an implemented MPEG-2 AAC decoder. The results showed that the computational complexity of the proposed method is reduced to 54% of that of the most up-to-date method.

• Journal of Korea Multimedia Society
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• v.19 no.8
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• pp.1310-1319
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• 2016

Face detection is the first step in a wide range of face applications. However, detecting faces in the wild is still a challenging task due to the wide range of variations in pose, scale, and occlusions. Recently, many deep learning methods have been proposed for face detection. However, further improvements are required in the wild. Another important issue to be considered in the face detection is the computational complexity. Current state-of-the-art deep learning methods require a large number of patches to deal with varying scales and the arbitrary image sizes, which result in an increased computational complexity. To reduce the complexity while achieving better detection accuracy, we propose a fully convolutional network-based face detection that can take arbitrarily-sized input and produce feature maps (heat maps) corresponding to the input image size. To deal with the various face scales, a multi-scale network architecture that utilizes the facial components when learning the feature maps is proposed. On top of it, we design multi-task learning technique to improve detection performance. Extensive experiments have been conducted on the FDDB dataset. The experimental results show that the proposed method outperforms state-of-the-art methods with the accuracy of 82.33% at 517 false alarms, while improving computational efficiency significantly.

• Journal of Korea Trade
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• v.25 no.7
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• pp.41-55
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• 2021

Purpose - This paper empirically investigates the relationship between the Economic Complexity Index (ECI) and the level of development. Moreover, this research attempts to discover the determinants of ECI in the globalization wave. Design/methodology - Our empirical model considers the relationship between ECI and the level of development in middle- and high-income economies from 1995 to 2010 by using systemic qualitative analysis, including OLS, fixed-effects, and system GMM. Next, this research used OLS regression to find the determinants of ECI. In particular, we compared the effects of different factors on ECI in the different development stages. Findings - Our main findings can be summarized as follows: 1. If the ECI increases by 1, it could lead to an increase of about 30% in the level of development in middle- and high-income economies. 2. Human capital plays an important role in the development of and increase in ECI. 3. GVC participation and outflow FDI enhance an increase in ECI, in particular in middle-income economies. 4. The development of manufacturing industries is helpful to increase ECI; however, middle-income economies should pay more attention to their comparative advantage industries. 5. R&D has positive effects on the ECI. Originality/value - To the best of our knowledge, this is the first paper that uses systemic qualitative analysis to investigate the relationship between ECI and the level of development. The paper provides suggestions for policy makers to increase ECI under the current wave of globalization, in particular in middle-income economies.

• Korean Institute of Interior Design Journal
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• v.22 no.3
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• pp.52-60
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• 2013

The contemporary concept of publicness is reinterpreted from the point of view of contemporary publicness. Contemporary perception of public space has now branched and grown into a multitude of non-traditional sites with a variety of programs in mind. In this study, the aim is to discuss how contemporary public library has been evolved as public space and how to create User-centered interaction. In the case of developed countries, the Public Libraries have showed the expected effects because they have more systematic and efficient plan. Also, these libraries are placed with each facility, not distributed separately. It promotes the accumulation of profit on the space and Increases the efficiency. They support more effectively users' activities through the linkages between each facility and create the active interaction between users. Formation of the various interactions and synergies between space had been induced. Publicity means that the state will relate a combination of a number of specific public area. In addition, open space, public place, shall be directed to: This place as one of the users in order to have meaning, must be equipped with the facilities and space to communicate and understand the local role. Methods of the study are to analyze the concept and role of the users with the concept of modern publicity, to examine the concept of multi-complexity of public libraries for the user-oriented publicness, to learn about the characteristics of public spaces in the public libraries that appear in the advanced countries, to examine how to affect these characteristics in the public libraries, and to suggest the possibility and the various application methods on the characteristics of a public space. In the end, the public libraries for the realization of the publicity, support program complexity such as education and culture, welfare facilities, and public service facilities. In the 21st century, these complexity to improve the quality of service in public libraries. These spaces can be an alternative to be kept comfortable in a more vibrant area, and can affect the social, natural, cultural, and environmental aspects of the physical environment and the objects and relationships, as well as expand.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.61-69
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• 2009

This paper presents the design results of a low complexity and high throughput LDPC encoder structure. In order to solve the high complexity problem of the LDPC encoder, a simplified matrix-vector multiplier is proposed instead of the conventional complex matrix-vector multiplier. The proposed encoder also adopts a partially parallel structure and performs column-wise operations in matrix-vector multiplication to achieve high throughput. Implementation results show that the proposed architecture reduces the number of logic gates and memory elements by 37.4% and 56.7%, compared with existing five-stage pipelined architecture. The proposed encoder also supports 800Mbps throughput at 40MHz clock frequency which is improved about three times more than the existing architecture.

• Journal of IKEEE
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• v.23 no.1
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• pp.207-213
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• 2019

In this paper, we propose a low-complexity feature detection algorithm for object tracking and present hardware architecture design and implementation results for real-time processing. The existing Shi-Tomasi algorithm shows good performance in object tracking applications, but has a high computational complexity. Therefore, we propose an efficient feature detection algorithm, which can reduce the operational complexity with the similar performance to Shi-Tomasi algorithm, and present its real-time implementation results. The proposed feature detector was implemented with 1,307 logic slices, 5 DSP 48s and 86.91Kbits memory with FPGA. In addition, it can support the real-time processing of 54fps at an operating frequency of 114MHz for $1920{\times}1080FHD$ images.

• Proceedings of the Korean Nuclear Society Conference
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• 2004.10a
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• pp.585-586
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• 2004