• 전기전자학회논문지
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• 제3권1호
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.361-364
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• 2003

In this paper, a high-resolution multibit sigma-delta modulator implemented in a.0.35-um CMOS technology is introduced. This modulator consists of two switched capacitor integrators, 3-bits A/D converter, and 3-bits D/A converter For the verification of the internal function blocks, HSPICE simulator is used. This circuit is normally operated at 130 MHz clock and the total power dissapation is 70 mW.

• 전기학회논문지
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• 제57권6호
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.1222-1225
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• 2004

This paper presents multibit Sigma-Delta ADC using noise-shaped dynamic element matching(DEM). 5-bit flash ADC for multibit quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. The DEM algorithm is implemented in such a way as to minimize additional delay within the feedback loop of the modulator Using this algorithm, distortion spectra from DAC linearity errors are shaped. Sigma Delta ADC achieves 82dB signal to noise ratio over 615H7z bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is designed to use 0.25um CMOS technology with 2.5V supply voltage and verified by HSPICE simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.507-508
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• 2006

High performance delta-sigma modulator is developed for audio-codec applications(i.e.. 16-bit resolution at a 20kHz signal bandwidth). The modulator is realized with fully-differential switched capacitor integrators. All stages employ a single-stage folded-cascode amplifier. The presented delta-sigma modulator when clocked at 3.2MHz achieves 85.2dB peak-SNDR and 94.8dB SNR. This modulator is designed in a SAMSUNG $0.18{\mu}m$ CMOS process. Finally, this paper shows the test setup and FFT result gained from delta-sigma modulator chip designed for audio applications.

• Journal of Semiconductor Engineering
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• 제2권1호
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.609-610
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• 2008

In this paper, a 110 dB, 1.024 MHz fourth-order single-loop Delta-Sigma sigma modulator has been presented with an over-sampling ratio of 128 and an overload factor of -6 dB for a bandwidth of 4 kHz. In particular, this ${\Sigma}-{\Delta}$ modulator is well suited for high accuracy measure systems. The whole modulator consumes only 3-mW from a single 3.3V supply in a $0.35-{\mu}m$ CMOS technology.

• 대한전자공학회논문지SD
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• 제44권6호
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• pp.50-59
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• 2007

[ $0.18-{\mu}m$ ] CMOS 공정에서 1.2-V 2차 Full-Feedforward 구조의 ${\Sigma}{\Delta}$ 모듈레이터를 설계하였다. Full-Feedforward 구조는 Op-Amp의 성능 요구치를 크게 경감시키기 때문에 저전압 저전력 ${\Sigma}{\Delta}$ 모듈레이터를 만들기에 적합한 구조로 세계적으로 많이 채택되고 있는 추세이다. 그리고, Top-Down 설계 기법을 적용하여 ${\Sigma}{\Delta}$ 모듈레이터를 설계하였는데, 이를 위하여 Op-Amp의 유한한 DC-Gain과 Bandwidth 등 여러 가지 비이상적 효과들을 모델링하여 전달함수를 유도하였다.

• 한국통신학회논문지
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• 제26권11A호
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• pp.1812-1819
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• 2001

본 논문에서는 OSR=25에서 1 [MHz] 신호 대역폭, 12-비트 해상도를 만족하는 SOSOC $\Sigma$-Δ길 변조기 설계를 위하여 아날로그 비이상성 허용범위를 조사하였다. 공급전압 3.3 [V]에서 사양을 만족하는 $\Sigma$-Δ 변조기 설계를 위하여 우선 저전압에 적합한 SOSOC $\Sigma$-Δ 변조기 모델과 이득계수를 구하였다. 그리고 아날로그 비이상성인 증폭기 유한한 이득, SR, 폐루프 극점, 스위치 ON 저항 그리고 캐패시터 부정합과 같은 $\Sigma$-Δ 변조기의 성능 저하 요인들을 이상적인 $\Sigma$-Δ 변조기 모델에 첨가하여 $\Sigma$-Δ 변조기의 성능 예측과 비 이상성의 허용범위를 규정하였다. 이를 토대로 사양을 만족하는 $\Sigma$-Δ 변조기 설계 시 $\Sigma$-Δ 변조기를 구성하는 회로의 사양에 대한 지침과 $\Sigma$-Δ 변조기의 성능을 예측 할 수 있다.

• Journal of electromagnetic engineering and science
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• 제8권2호
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• pp.76-83
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• 2008

A low power(9 mW) highly-digitized 2.4 GHz receiver for sensor network applications(IEEE 802.15.4 LR-WPAN) is realized by a $0.18{\mu}m$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time(CT) bandpass L:tl modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $\Sigma\Delta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range(DR) of the over-all system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.