DOI QR코드

DOI QR Code

A 9 mW Highly-Digitized 802.15.4 Receiver Using Bandpass ∑Δ ADC and IF Level Detection

  • Kwon, Yong-Il (SAMSUNG Electro-Mechanics, Central R&D Institute) ;
  • Park, Ta-Joon (SAMSUNG Electro-Mechanics, Central R&D Institute) ;
  • Lee, Hai-Young (Department of Electronics Engineering, Ajou University)
  • Published : 2008.06.30

Abstract

A low power(9 mW) highly-digitized 2.4 GHz receiver for sensor network applications(IEEE 802.15.4 LR-WPAN) is realized by a $0.18{\mu}m$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time(CT) bandpass L:tl modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $\Sigma\Delta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range(DR) of the over-all system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply.

Keywords

References

  1. IEEE 802.15.4 WPAN-LR standard
  2. P. Kathleen, A. C. M. Peter, 'A continuous time sigma- delta ADC with increased immunity to interferes', IEEE J. Solid-State Circuits, vol. 39, no. 12, Dec. 2004
  3. B. Razavi, RF Microelectronics, Prentice Hall Communications Engineering and Emerging Technologies Series, 1998
  4. R. Schreier, G. C. Temes, Understanding Delta-Sigma Data Converters, John Wiley & Sons, Inc., 2005
  5. M. Ortmanns, F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion, Springer, 2006
  6. MatLab tools (ver 7.0) : The MathWorks
  7. S. N. Norman, Control System Engineering, John Wiley & Sons, Inc., 2004
  8. S. Paton, A. Digianmenico, L. Hernadez, and A. Wiesbauer, 'A 70 mW 300 MHz CMOS continuous- time sigma-delta ADC with 15 MHz bandwidth and 11-bit of resolution', IEEE J. Solide State Circuits 39, 1056-1063, Jul. 2004 https://doi.org/10.1109/JSSC.2004.829925
  9. F. Gerfers, M. Ortmanns, and Y. Manoli, 'A 1.5 V 12-bit power efficient continuous-time third order sigma-delta modulator', IEEE J. Solid-State Circuits, vol. 38, pp. 1343-1352, Aug. 2003 https://doi.org/10.1109/JSSC.2003.814432
  10. P. Leroux, J. Janssens, and M. Steyaert, 'A 0.25 _m CMOS LNA with local impedance matching', Dept. Elect. Eng., Master's thesis, K.U. Leuven, Leuven, Belgium, 1999
  11. F. Esfahani, P. Basedau, R. Ryter, and R. Becker, 'An 82 dB CMOS continuous-time complex bandpass sigma-delta ADC for GSM/EDGE', in Proc. ISCAS Int. Circuits and System Symp., vol. 1, pp. 1049-1052, May 2003
  12. H. K. C. Issac, '70 MHz CMOS bandpass sigma- delta analog to digital converter for wireless receivers', A thesis for Ph.D., The Hong Kong University of Science and Technology, Aug. 1999
  13. F. Henkel, U. Langmann, A. Hanke, S. Heinen, and E. Wagner, 'A 1-MHz bandwidth second-order continuous time quadrature bandpass sigma delta modulator for Low-IF radio receivers', IEEE J. Solid- State Circuits, vol. 37, no. 12, pp. 1628-1635, Dec. 2002 https://doi.org/10.1109/JSSC.2002.804332
  14. Circuit simulation tools by Cadence Company
  15. K. Kimura, 'A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs', IEEE J. Solid- State Circuits, vol. 28, pp. 78-83, Jan. 1993 https://doi.org/10.1109/4.179206
  16. J. H. Lim, K. S. Cho, and Y. I. Kwon, 'A fully integrated 2.4 GHz IEEE 802.15.4 transceiver for Zigbee applications', in Proc. Asia-Pacific Microwave Conf., vol. 3, pp. 1779-1782, Dec. 2006