• 한국펄프종이공학회:학술대회논문집
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• 한국펄프종이공학회 2003년도 춘계학술발표논문집
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• pp.70-79
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• 2003

Paper coating can give smoothness surface and good printability to uncoated paper. Macro roughness of base paper would be decreasing its groove and grit in view of side. Nevertheless its improving effect for paper, some kind of problem is showing in the fine coated paper. Especially, back trap mottle is one of serious problems in printing with fine coated paper. Printers can not adjust conditions to overcome the problem. Also large amounts of paper can be rejected. There are many factors that influence back trap mottle. However it is not clear what the important parameters are in back trap mottle. Back trap mottle has some relationship with ink setting but good guidelines are not clear. Back trap mottle has been linked to non-uniform ink setting. We do not know how much variation in setting we can tolerate. Other mottle issues such as micro-picking and ink refusal are still common. This paper was prepared to identify correlation with ink setting and delta ink density obtained from experiment and then tried to find out some relationships with ink setting and back trap mottle. Basically fine calcium carbonate and ciay was used for main components and coarse calcium carbonate was mixed in two fine pigments to change its porosity and ink acceptance. Micro ink tack force at KRK printing tester was adapted to measure ink setting rate. KRK units were used for back trap mottle simulation and two printed samples were prepared to check delta ink density. Clay base coating has more fast ink setting time than calcium carbonate's though smoothness of clay was better than calcium carbonate. It could be explained by that clay has finer pore in its coating than calcium carbonate. DID(delta ink density) has shown a good correlation with ink setting time from micro ink tack. The total pore volume of coating layer did not match with ink setting and DID. From the results we might conclude coating that has fine pore size around 0.05 ${\mu}m$ can be exposed to high possibility of back trap mottle.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.185-190
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• 2016

A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.

• Ocean Science Journal
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• 제40권3호
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• pp.167-176
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• 2005

A time-series sediment trap was deployed at 1,034 m water depth in the eastern Bransfield Strait for a complete year from December 25, 1998 to December 24, 1999. About 99% of total mass flux was trapped during an austral summer, showing distinct seasonal variation. Biogenic particles (biogenic opal, particulate organic carbon, and calcium carbonate) account for about two thirds of annual total mass flux $(49.2\;g\;m^{-2})$, among which biogenic opal flux is the most dominant (42% of the total flux). A positive relationship (except January) between biogenic opal and total organic carbon fluxes suggests that these two variables were coupled, due to the surface-water production (mainly diatoms). The relatively low $\delta^{13}C$ values of settling particles result from effects on C-fixation processes at low temperature and the high $CO_2$ availability to phytoplankton. The correspondingly low $\delta^{l5}N$ values are due to intense and steady input of nitrates into surface waters, reflecting an unlikely nitrate isotope fractionation by degree of surface-water production. The $\delta^{l5}N$ and $\delta^{l3}C$ values of sinking particles increased from the beginning to the end of a presumed phytoplankton bloom, except for anomalous $\delta^{l5}N$ values. Krill and the zooplankton fecal pellets, the most important carriers of sinking particles, may have contributed gradually to the increasing $\delta^{l3}C$ values towards the unproductive period through the biomodification of the $\delta^{l3}C$ values in the food web, respiring preferentially and selectively $^{12}C$ atoms. Correspondingly, the increasing $\delta^{l5}N$ values in the intermediate-water trap are likely associated with a switch in source from diatom aggregates to some remains of zooplankton, because organic matter dominated by diatom may be more liable and prone to remineralization, leading to greater isotopic alteration. In particular, the tendency for abnormally high $\delta^{l5}N$ values in February seems to be enigmatic. A specific species dominancy during the production may be suggested as a possible and speculative reason.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

• 한국전기전자재료학회논문지
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• 제22권11호
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• pp.949-955
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• 2009

In this study, we investigated the effects of Cr dopant (1.0 at% $Cr_2O_3$ sintered at $1000^{\circ}C$ for 1 h in air) on the bulk trap (i.e. defect) and interface state levels of ZnO using dielectric functions ($Z^*$, $M^*$, $Y^*$, $\varepsilon^*$, and $tan{\delta}$), admittance spectroscopy (AS), and impedance-modulus spectroscopy (IS & MS). For the identification of the bulk trap levels, we examine the zero-biased admittance spectroscopy and dielectric functions as a function of frequency and temperature. Impedance and electric modulus spectroscopy is a powerful technique to characterize grain boundaries of electronic ceramic materials as well. As a result, three kinds of bulk defect trap levels were found below the conduction band edge of ZnO in 1.0 at% Cr-doped ZnO (Cr-ZnO) as 0.11 eV, 0.21 eV, and 0.31 eV. The overlapped defect levels ($Zn^{..}_i$ and $V^{\cdot}_0$) in admittance spectra were successfully separated by the combination of dielectric function such as $M^*$, $\varepsilon^*$, and $tan{\delta}$. In Cr-ZnO, the interfacial state level was about 1.17 eV by IS and MS. Also we measured the resistance ($R_{gb}$) and capacitance ($C_{gb}$) of grain boundaries with temperature using impedance-modulus spectroscopy. It have discussed about the stability and homogeneity of grain boundaries using distribution parameter ($\alpha$) simulated with the Z"-logf plots with temperature.

• 대한전자공학회논문지
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• 제25권11호
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• pp.1294-1303
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• 1988

광 유도 전류 천이 (photo-induced current transient)방법으로 측정한 SI GaAs의 전자와 정공 trap이 갖을 수 있는 activation energy({\Delta}E_r)의 범위는 0.16$\pm$ 0.01eV에서 0.98$\pm$ 0.01eV까지 분포되어 있다. SI Undoped GaAs가 SI GaAs : Cr 보다 깊은 준위의 수가 적음을 확인 하였다. Trap의 열적인 capture cross section과 농도를 평가 하였고, 약간의 trap은 SI GaAs 성장시에 발생될 수 있는 결함과 관련되어 있음을 확인하였다. 특히 SI GaAs에서 보상 level로 작용하는 Cr과 “0” level를 좀 더 정확하게 측정하기 위하여 서로 다른 측정방법을 사용하여 측정한 결과를 각기 비교 검토 하였다. 즉, PICT측정, 상온 이상의 온도에서 측정한 Hall data 및 광전류 spectra data 등을 비교 검토 하였으며, 보상 level은 격자 결합이 매우 약함을 확인할 수 있었다. Hall data를 computer로 분석한 결과 중성 불순물 scattering이 측정 온도 범위에서 매우 중요한 역할을 하고 있음을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1991년도 추계학술대회 논문집
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• pp.44-47
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• 1991

Electron injection and memory retention chracteristics of the MNOS devices with thin oxide layer of 23${\AA}$ thick and silicon nitride layer of 1000${\AA}$ thick which are fabricated for this experiment. As a result, pulse amplitude increase oxide current is dominated in linearly increasing region of $\Delta$V$\_$FB/the decreasing region after saturation was due to the increased silicon nirtide current. In low pulse ampiltude $\Delta$V$\_$FB/ is not variated on temperature, but as temperature and pulse amplitude increase. $\Delta$V$\_$FB/ is decreased after saturation. And the decay rate during 10$^4$sec after electron injection was ohiefly dominated by the back tunneling of emission from memory trap to silicon. Memory retention characteristics in V$\_$FB/ stage was better than that of OV retention regardless of injection conditions.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• Transactions on Electrical and Electronic Materials
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• 제18권1호
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• Korean Chemical Engineering Research
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• 제48권6호
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• pp.737-740
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• 2010

높은 누설 전류와 문턱 전압의 이동은 비정질 실리콘(a-Si:H) 트랜지스터(TFT)의 단점이다. 이러한 특성은 게이트 절연체와 활성층 박막의 막 특성, 표면 거칠기와 공정 조건에 따라 영향을 받는다. 본 연구의 목적은 누설 전류와 문턱 전압의 특성을 개선하는데 목적이 있다. 게이트 절연체의 공정 조건에 대해서는 질소를 증가한 증착 공정 조건을 적용하였고, 활성층의 공정 조건에 대해서는 산소를 증가한 공정 조건을 적용하여 전자 포획을 감소시키고 박막의 밀도를 증가시켰다. $I_{off}$는 $65^{\circ}C$ 조건하에서 1.01 pA에서 0.18pA로, ${\Delta}V_{th}$는 -1.89 V에서 -1.22V로 개선되었다.