• 대한의용생체공학회:의공학회지
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• 제17권3호
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• pp.395-401
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• 1996

In this paper a new neural network model, time delayed counterpropagation neural networks (TDCPN) which have high recognition rate and short total learning time, is proposed for electromyogram(EMG) recognition. Signals the proposed model increases the recognition rates after learned the regional temporal correlation of patterns using time delay properties in input layer, and decreases the learning time by using winner-takes-all learning rule. The ouotar learning rule is put at the output layer so that the input pattern is able to map a desired output. We test the performance of this model with EMG signals collected from a normal subject. Experimental results show that the recognition rates of the suggested model is better and the learning time is shorter than those of TDNN and CPN.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.525-526
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• 2008

For measuring nonlinear Vehicle Modeling based on 7-Depth Sensor, the neural networks are proposed m adaptive and in realtime. The structure of it is similar to recurrent neural networks; a delayed output as the input and a delayed error between the output of plant and neural networks as a bias input. In addition, we compute the desired value of hidden layer by an optimal method instead of transfering desired values by backpropagation and each weights are updated by RLS(Recursive Least Square). Consequently, this neural networks are not sensitive to initial weights and a learning rate, and have a faster convergence rate than conventional neural networks. This new neural networks is Error Estimated Neural Networks. We can estimate nonlinear models in realtime by the proposed networks and control nonlinear models.

• International Journal of Control, Automation, and Systems
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• 제3권4호
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• pp.646-647
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• 2005

A recently published paper demonstrates the utility of allowing delays in state estimators for linear systems with unknown inputs. In this note, we point out an error in the derivation of the estimator.

• ETRI Journal
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• 제29권6호
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• pp.835-837
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• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1986년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 17-18 Oct. 1986
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• pp.571-575
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• 1986

The squirrel-cage induction motor can be characterized as a nonlinear and multi-input, multi-output system, and has the unmeasurable states which are the rotor currents. In this paper, the time-delayed output feedback method is applied to the speed control of induction motor driven by the current-controlled PWM inverter and its performance is investigated by using the computer simulation.

• 한국도로학회논문집
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• 제14권6호
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• pp.131-138
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• 2012

PURPOSES : Two-lane highways have one lane in each direction, and lane changing and passing maneuvers take place in the opposing lane depending on the availability of passing sight distance. 2001 Korea Highway Capacity Manual (KHCM) is classified into two classes of two-lane highways (Type I, II), and average travel speed and time-delayed rate are used as measures of effectiveness (MOEs). However, since existing two-lane highways have both uninterrupted and interrupted traffic flow-system elements, a variety of free-flow speeds exhibits in two-lane highways. In addition, it is necessary to check if the linear-relationship between volumes and time-delayed rate is appropriate. Then, this study is to reestablish the relationship between average travel speed, time-delayed rate, and flow. METHODS : TWOPAS model was selected to conduct this study, and the free-flow speeds of passenger cars and the percentage of following vehicles observed in two-lane highways were applied to the model as the input. The revised relationships were developed from the computer simulation. RESULTS : In the revised average travel speed vs. flow relationship, the free-flow speed of 90km/h and 70km/h were added. It shows that the relationship between time delayed-rate and flow appeared to be appropriate with the log-function form and that there was no difference in time-delayed rate between the free flow speeds. In addition to revise the relationships, the speed prediction model and the time-delayed rate prediction model were also developed. CONCLUSIONS : The revised relationships between average travel speed, time-delayed rate, and flow would be useful in estimating the Level of Service(LOS) of a two-lane highway.

• 전자공학회논문지A
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• 제33A권11호
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• 전기전자학회논문지
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• 제27권3호
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• pp.273-279
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• 2023

이미지처리 하드웨어에서 이미지 필터링을 진행할 때 line memory의 사용은 필수적이다. line memory에 입력 데이터를 저장한 후 저장된 데이터를 사용하기 위해 동기를 맞춘 후 필터링을 진행한다. 이때 동기를 맞추기 위해 동기 발생기를 사용한다. 기존 동기 발생기의 경우 입력 동기 신호를 입력으로 들어오는 이미지의 1행만큼 지연시킨다. 만약 2행만큼 지연된 신호를 얻기 위해서는 모듈 2개를 연결하여 사용해야 한다. 해당 방식으로 하드웨어 설계 시 하드웨어의 크기가 커져 효율적으로 설계할 수 없다. 따라서 본 논문에서는 finite state machine을 추가하는 방식을 사용하여 여러 종류의 지연 신호를 생성하는 동기 발생기를 제안한다. 하드웨어 설계는 Verilog HDL로 코딩하였으며, field programmable gate array 보드를 이용하여 이미지처리 하드웨어에 적용하여 성능을 검증하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권5호
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• pp.2124-2141
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• 2018

Recent studies have revealed the efficacy of incorporating delayed channel state information at transmit side (CSIT) in transmission scheme design. This paper focuses on transmit precoder design to maximize the ergodic sum-rate in a two-user Multiple-Input Single-Output (MISO) system with delayed and statistical CSIT. A new transmit strategy which precodes signals in all transmit slots is proposed in this paper, denoted as all time-slots precoding Alternative MAT (AAMAT). There is a common procedure in conventional delayed-CSIT based schemes, which is retransmitting the overheard interferences. Since the retransmitting signal is intended to both users, all previous schemes tend to use only one antenna. We however figure out an improvement in spectral efficiency could be realized if all antennas can be utilized. In this paper, we detail the design of the procoder which enabling all antennas and also we compute a lower bound of the ergodic sum-rate in an ideal condition. In addition, simulation results demonstrate the superiority of our proposed scheme.

• 제어로봇시스템학회논문지
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• 제11권1호
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• pp.1-8
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• 2005

A new discretization algorithm for nonlinear systems with delayed input is proposed. The algorithm is represented by Taylor series expansion and ZOH assumption. This method is applied to the sampled-data representation of a nonlinear system with the time-delay input. Additionally, the delay in input is time varying and its amplitude is bounded. The maximum time-delay in input is assumed to be two sampling periods. The mathematical expressions of the discretization method are presented and the ability of the algorithm is tested for some of the examples. The computer simulation proves the proposed algorithm discretizes the nonlinear system with the variable time-delay input accurately.