Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

Design of a Variable-Mode Sync Generator for Implementing Digital Filters in Image Processing

이미지처리에서 디지털 필터를 구현하기 위한 가변모드 동기 발생기의 설계

  • Semin Jung (Dept. of Electronics Engineering, Dong-A University) ;
  • Si-Yeon Han (Dept. of Electronics Engineering, Dong-A University) ;
  • Bongsoon Kang (Dept. of Electronics Engineering, Dong-A University)
  • Received : 2023.08.25
  • Accepted : 2023.09.20
  • Published : 2023.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

The use of line memory is essential for image filtering in image processing hardware. After input data is stored in line memory, filtering is performed after synchronization to use the stored data. A sync generator is used for synchronization, and in the case of a conventional sync generator, the input sync signal is delayed by one row of the input image. If a signal delayed by two rows is required, it is necessary to connect two modules. This approach increases the size of the hardware and cannot be designed efficiently. In this paper, we propose a sync generator that generates multiple types of delayed signals by adding a finite state machine. The hardware design was coded in Verilog HDL, and performance is verified by applying it to image processing hardware using field programmable gate array board.

이미지처리 하드웨어에서 이미지 필터링을 진행할 때 line memory의 사용은 필수적이다. line memory에 입력 데이터를 저장한 후 저장된 데이터를 사용하기 위해 동기를 맞춘 후 필터링을 진행한다. 이때 동기를 맞추기 위해 동기 발생기를 사용한다. 기존 동기 발생기의 경우 입력 동기 신호를 입력으로 들어오는 이미지의 1행만큼 지연시킨다. 만약 2행만큼 지연된 신호를 얻기 위해서는 모듈 2개를 연결하여 사용해야 한다. 해당 방식으로 하드웨어 설계 시 하드웨어의 크기가 커져 효율적으로 설계할 수 없다. 따라서 본 논문에서는 finite state machine을 추가하는 방식을 사용하여 여러 종류의 지연 신호를 생성하는 동기 발생기를 제안한다. 하드웨어 설계는 Verilog HDL로 코딩하였으며, field programmable gate array 보드를 이용하여 이미지처리 하드웨어에 적용하여 성능을 검증하였다.

Keywords

Acknowledgement

This work was supported by the Ministry of Education of the Republic of Korea and the National Research Foundation of Korea(NRF-2023R1A2C1004592)

References

  1. H.-S. Park, "Single SRAM Based Line Memory System for Providing Column Vectors of 2D Filtering," Journal of KIIT, vol.12, no.4, pp.137-143, 2014. DOI: 10.14801/kiite.2014.12.4.137
  2. M. Azizabadi and A. Behrad, "Design and VLSI implementation of new hardware architectures for image filtering," 2013 8th Iranian Conference on Machine Vision and Image Processing, 2013. DOI: 10.1109/IranianMVIP.2013.6779960
  3. Ngo. D, S. Lee, U.-J. Kang, T. M. Ngo, G.-D. Lee and B. Kang, "Adapting a Dehazing System to Haze Conditions by Piece-Wisely Linearizing a Depth Estimator," Sensors, vol.22, no.5, pp.1957-1981, 2022. DOI: 10.3390/s22051957
  4. U.-J. Kang and B. Kang, "Hardware Implementation of Fog Feature Based on Coefficient of Variation Using Normalization," Journal of the lorea Institute of Information and Communication Enginerring, vol.25, no.6, pp.819-824, 2021.
  5. S. Lee and B. Kang, "A 4K-Capable Hardware Accelerator of Haze Removal Algorithm using Haze-relevant Features," Journal of information and communication convergence engneering, vol.20, no.3, pp. 212-218, 2022. DOI: 10.56977/jicce.2022.20.3.212
  6. A. Sengupta and M. Rathor, "Obfuscated hardware accelerators for image processing filters-Application specific and functionally reconfigurable processors," IEEE Transactions on Consumer Electronics, vol.66, no.4, 2020. DOI: 10.1109/TCE.2020.3027760
  7. Shambhu Sharan and S.P. Tiwari, "Products of Mealy-type Rough Finite State Machine," 2012 National Conference on Computing and Communication Systems, 2012. DOI: 10.1109/NCCCS.2012.6412988
  8. W. Jang, J. Kim, S. Lee, B. Kwak and B. Kang, "Hardware Implementation of 2D-CZP Pattern for System verification," 2007 Autumn Annual Conference of IEIE, vol.30, no.2, pp.597-598, 2007.
  9. Mentor Graphics, "ModelSimⓡ User's Manual," http://microsemi.com/document-portal/doc_view/131619-modelsim-user
  10. IEEE Std 1364-2005 (Revision of IEEE Std 1374-2001), "IEEE Standard for Verilog Hardware Description Language," 2006. DOI: 10.1109/IEEESTD.2006.99495
  11. Xilinx, "ZCU106 Board User Guide," https://docs.xilinx.com/v/u/en-US/ug1244-zcu106-evalbd