• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1695-1702
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• 2001

This paper describes a design of CMOS infrared (IR) wireless data link IC which can be used in IrDA(Infrared Data Association) application from 4 Mb/s to 100 Mb/s The implemented chip consists of variable gain transimpedance amplifier which has a gain range from 60 dB to 100 dB, AGC (automatic gain control) circuits, AOC(automatic offset control) loop, 4 PPM (pulse position modulation) modulator/demodulator and DLL(delay locked loops). This infrared optical link If was implemented using commercial 0.25 um 1-poly 5-metal CMOS process. The chip consumes 25 mW at 100 Mb/s with 2.5 V supply voltage excluding buffer amplifier. The die area of prototype IC is 1.5 mm $\times$ 1 mm.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.325-332
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• 2004

In this paper, we propose a new DSSS-QPSK baseband modem receiver structure. A general receiver consists of matched filter, do-spreader, and DLL(Delay Locked Loop). In this paper, the matched filter plays a role of the do-spreader using the structure similarities between the matched filter and the de-spreader. As a result of the new receiver architecture, we can reduce the computational expenses and get the simpler receiver structure. This result can be used as an important part in designing the high speed modem. And, through the computer simulation and the experiment with the proposed architecture, we show that the proposed receiver structure yields fast operation speed and simple overall architecture.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• Current Optics and Photonics
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• v.2 no.6
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• pp.563-567
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• 2018

We propose and experimentally demonstrate a simple tunable photonic microwave band-pass filter with high resolution using a reflective semiconductor optical amplifier (RSOA) and an optical time-delay line. The RSOA is used as a gain medium for generating cross-gain modulation (XGM) effect as well as an optical source. The optical source provides narrow spectral width by self-injection locking the RSOA in conjunction with a partial reflection filter with specific center wavelength. Then, when the RSOA is operated in the saturation region and the modulated recursive signal is injected into the RSOA, the recursive signal is inversely copied to the injection locked optical source due to the XGM effect. Also, the tunability of the passband of the proposed microwave filter is shown by controlling an optical time-delay line in a recursive loop.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.501-504
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• 2000

In this paper, performance of a pseudonoise (PN) code tracking loop is analyzed and simulated for a direct-sequence/code-division multiple access ( DS/CDMA) system with imperfect power control in a multipath fading channel. A noncoherent first-order delay-locked loop (DLL) is considered as a PN code tracking loop. Power control error is modeled as a log-normally distributed random variable. From the simulation results, it is shown that for smaller discriminator offset, tracking jitter performance is improved while MTLL performance is degraded. It is shown that large power control error and heavy shadowing substantially degrade the PN tracking performance. The analysis in this paper can be applicable to design of PN code tracking loop for a DS/CDMA system.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.