• Journal of the Korean Society of Safety
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• v.21 no.4 s.76
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• pp.66-72
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• 2006

An accurate knowledge of the AITs(autoignition temperatures) is important in developing appropriate prevention and control measures in industrial fire protection. The measurement of AITs are dependent upon many factors, namely initial temperature, pressure, vessel size, fuel/air stoichiometry, catalyst, concentration of vapor, ignition delay time. The values of the AITs used process safety are normally the lowest reported, to provide the greatest margin of sefety. This study measured the AITs of o-xylene+n-pentanol system from ignition delay time by using ASTM E659-78 apparatus. The experimental AITs of o-xylene and n-pentanol were $480^{\circ}C\;and\;285^{\circ}C$, respectively. The experiment AITs of o-xylene+n-pentanol system were a good agreement with the calculated AITs by the proposed equations with a few A.A.D.(average absolute deviation).

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.4
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• pp.324-332
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• 2016

In this paper, the terminal homing loop with a IIR-type strapdown seeker and a roll rate gyroscope is proposed. Basically, the proposed homing loop is based on the look-angle-control guidance. Since the range of the seeker is strictly limited, the missile is delivered to a point to lock the target on the seeker via non-guided flight during the midcourse guidance. The non-standard firing table is developed to compensate the wind and the target movement. To secure the delay margin is very important to prevent the instability of the homing loop when the time delay of the seeker is included. To validate the proposed homing loop, the 6-DOF nonlinear simulation is performed, and the Monte-Carlo simulation is also done for checking the robustness for the various kinds of uncertainty.

• Nuclear Engineering and Technology
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• v.48 no.3
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• pp.684-701
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• 2016

The Gaussian process model (GPM) is a flexible surrogate model that can be used for nonparametric regression for multivariate problems. A unique feature of the GPM is that a prediction variance is automatically provided with the regression function. In this paper, we estimate the safety margin of a nuclear power plant by performing regression on the output of best-estimate simulations of a large-break loss-of-coolant accident with sampling of safety system configuration, sequence timing, technical specifications, and thermal hydraulic parameter uncertainties. The key aspect of our approach is that the GPM regression is only performed on the dominant input variables, the safety injection flow rate and the delay time for AC powered pumps to start representing sequence timing uncertainty, providing a predictive model for the peak clad temperature during a reflood phase. Other uncertainties are interpreted as contributors to the measurement noise of the code output and are implicitly treated in the GPM in the noise variance term, providing local uncertainty bounds for the peak clad temperature. We discuss the applicability of the foregoing method to reduce the use of conservative assumptions in best estimate plus uncertainty (BEPU) and Level 1 probabilistic safety assessment (PSA) success criteria definitions while dealing with a large number of uncertainties.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.21-29
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• 2002

This paper describes a high resolution DLL(Delay Locked Loop) using all digital circuits. The proposed architecture is based on the three stage of coarse, fine and ultra fine phase tuning block which has a phase detector, selection block and delay line respectively. The first stage, the ultra fine phase tuning block, is tune to accomplish high resolution using a vernier delay line. The second and third stage, the coarse and fine tuning block, are tuning the phase margin of Unit Delay using the delay line and are similar to each other. It was simulated in 0.35um CMOS technology under 3.3V supply using HSPICE simulator. The simulation result shows the phase resolution can be down to lops with the operating range of 250MHz to 800MHz.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.293-316
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• 2006

[ $\blacksquare$ ] I/O Signal $\square$ We see adequate margin for the RC B design $\square$ Minimum ODW value is 328ps using Ac to DC measurement for the read case. $\square$ Minimum ODW value is 350ps using AC to DC mesurement method for the write case. $\blacksquare$ CLK Signal $\square$ The slew-rate decreases when the Cterm value increases $\square$ Lower slew-rate could effect delay and jitter. $\square$ There are some ldge issues during transitions with lower Cterm and without Cterm. $\square$ Our recommendation for the Cterm value range is between 1.5pF to 2.4pF. $\blacksquare$ ADD/CMD/Ctrl Signal $\square$ High output slew-rate at low VDD causes ring back that reduces voltage margin because of x-talk. $\square$ 30ohm Rterm for the CTRL signal shows a better signal integrity result compared to 36ohm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.509-520
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• 1992

AIGaAs /GaAs HBT OR /NOR gate. which can be used for high speed digital system was designed. Equivalent circuit parameters of HBT were obtained from Gummel-Poon's model and direct extraction method. Simulation results with PSPI CE showed that propagation delay time and cutoff toggle frequency of designed gate were 25ps and 200Hz, respectively. the designed gate exhibited superior properties to the recently reported HBT ECL and MESFET SCFL when considering the fan-out characteristics and noise margin.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2370-2378
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• 2009

The enhanced phase angle estimation algorithm is essential to supply the power stably under synchronizing with grid source. In this paper, we are proposed the novel phase angle estimation algorithm and verified the validity of proposed method as simulation with PSIM and experiments. We sort the harmonics element using high-pass filter(HPF) that have the cut-off frequency below basic element and make reverse d-q transformation. So, it can be restored the harmonics element at stationary axis, and we can get the fundamental voltage element of AC grid. Proposed PLL method have a rapid responsibility and a large margin at controller design than conventional method because it have a small phase delay and a sufficient controller gain margin. And, it can reduce the error of voltage rms value and axis transformation according to robust PLL algorithm against the harmonic and phase unbalance.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.12
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• pp.1302-1307
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• 1991

This paper presents robustness properties of Kalman filters for linear time-invariant systems with delays in both the state and the output. The circle condition concerning the return difference matrix is derived. From the circle condition, it can be seen that the Kalman filter guarantees such nondivergence margins as (1/2,$\infty$) gain margin and $\pm$60$^{\circ}$phase margin, which are the same as those for ordinary systems. The results in this paper might be expected to make theoretical background on extending the LQG/LTR method to systems with delay in the output.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.167-174
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• 2015

This study describes how digital time delay deteriorates control performance in zero voltage switching (ZVS) phase-shifted full bridge (PSFB) converter. The small-signal model of the ZVS PSFB converter is derived from the buck-converter small-signal model. Digital time delay effects have been considered according to the digital sampling methods. The analysis verifies that digital time delays reduce the stability margin of the converter, and the double sampling technique exhibits better performance than the single sampling technique. Both simulation and experimental results based on 250 W ZVS PSFB confirm the validity of the analyses performed in the study.

• Journal of Sensor Science and Technology
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• v.28 no.1
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• pp.17-22
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• 2019

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.